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PI7C7300A 3-PORT PCI-to-PCI BRIDGE
REVISION 1.09
2380 BERING DRIVE, SAN JOSE, CA 95131 TELEPHONE: 1-877-PERICOM (1-877-737-4266) FAX: 408-435-1100 EMAIL: SOLUTIONS@PERICOM.COM INTERNET: HTTP://WWW.PERICOM.COM
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
LIFE SUPPORT POLICY Pericom Semiconductor Corporation's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC. 1. Life support devices or systems are devices or systems which: a) are intended for surgical implant into the body or b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
REVISION HISTORY
Revision 1.01 Date 9/25/01 Description Corrected the description for bits 4:2 in both Configuration register 1 and configuration register 2 at offset 40h (Diagnostic/ Chip Control Register). Bit 4 controls the memory read and flow-through and bits 3:2 are reserved. Updated jumper setting/descriptions for the Evaluation Board User's Manual. Updated Sheet 1 of the schematics. 1.02 1.03 10/25/01 10/29/01 Added more description to Primary Reset. Replaced Preliminary Information with Advanced Information. Corrected Bit 30 of Secondary Status Register to read Received instead of Signaled Changed email address from nolimits@pericom.com to
solutions@pericom.com.
1.04 1.05 1.06 11/12/01 12/19/01 06/04/02 Corrected PBGA Pin List (S2_AD[28], S1_CLKOUT[7:0] and S2_CLKOUT[7:0] incorrect) Corrected P_AD[27,26] in section 3.2 P_AD[27] should be V8 instead of U8, and P_AD[26] should be U8 instead of V8. TBD references for TDELAY in sections 17.4 and 17.5 removed. TBD references removed for power consumption and supply current in section 17.6. Ambient temperature corrected in section 0 (maximum ratings) 1.07 08/22/02 Revised TSKEW in section 17.4 and 17.5 Added web reference to Thermal Characteristics in section 0 1.08 1.09 09/09/03 09/25/03 Corrected part number references from PI7C7300 to PI7C7300A. Added back PO signal type description on section 3.1
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
TABLE OF CONTENTS
1 2 3 INTRODUCTION .............................................................................................................................. 11 BLOCK DIAGRAM........................................................................................................................... 12 SIGNAL DEFINITIONS ................................................................................................................... 13 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 SIGNAL TYPES .......................................................................................................................... 13 PRIMARY BUS INTERFACE SIGNALS ................................................................................... 13 SECONDARY BUS INTERFACE SIGNALS............................................................................. 15 CLOCK SIGNALS....................................................................................................................... 17 MISCELLANEOUS SIGNALS ................................................................................................... 17 COMPACT PCI HOT-SWAP SIGNALS..................................................................................... 17 JTAG BOUNDARY SCAN SIGNALS........................................................................................ 18 POWER AND GROUND............................................................................................................. 18 PI7C7300A PBGA PIN LIST ....................................................................................................... 18
PCI BUS OPERATION ..................................................................................................................... 21 4.1 TYPES OF TRANSACTIONS..................................................................................................... 21 4.2 SINGLE ADDRESS PHASE ....................................................................................................... 22 4.3 DUAL ADDRESS PHASE........................................................................................................... 22 4.4 DEVICE SELECT (DEVSEL#) GENERATION......................................................................... 22 4.5 DATA PHASE ............................................................................................................................. 22 4.6 WRITE TRANSACTIONS .......................................................................................................... 23 4.6.1 MEMORY WRITE TRANSACTIONS.................................................................................... 23 4.6.2 MEMORY WRITE AND INVALIDATE TRANSACTIONS.................................................... 24 4.6.3 DELAYED WRITE TRANSACTIONS ................................................................................... 24 4.6.4 WRITE TRANSACTION ADDRESS BOUNDARIES ............................................................ 25 4.6.5 BUFFERING MULTIPLE WRITE TRANSACTIONS........................................................... 26 4.6.6 FAST BACK-TO-BACK WRITE TRANSACTIONS .............................................................. 26 4.7 READ TRANSACTIONS ............................................................................................................ 26 4.7.1 PREFETCHABLE READ TRANSACTIONS......................................................................... 26 4.7.2 NON-PREFETCHABLE READ TRANSACTIONS ............................................................... 27 4.7.3 READ PREFETCH ADDRESS BOUNDARIES.................................................................... 27 4.7.4 DELAYED READ REQUESTS ............................................................................................. 28 4.7.5 DELAYED READ COMPLETION WITH TARGET ............................................................. 28 4.7.6 DELAYED READ COMPLETION ON INITIATOR BUS..................................................... 29 4.7.7 FAST BACK-TO-BACK READ TRANSACTION.................................................................. 30 4.8 CONFIGURATION TRANSACTIONS ...................................................................................... 30 4.8.1 TYPE 0 ACCESS TO PI7C7300A......................................................................................... 30 4.8.2 TYPE 1 TO TYPE 0 CONVERSION ..................................................................................... 31 4.8.3 TYPE 1 TO TYPE 1 FORWARDING.................................................................................... 32 4.8.4 SPECIAL CYCLES ............................................................................................................... 33 4.9 TRANSACTION TERMINATION ............................................................................................. 34 4.9.1 MASTER TERMINATION INITIATED BY PI7C7300A ....................................................... 35 4.9.2 MASTER ABORT RECEIVED BY PI7C7300A .................................................................... 35 4.9.3 TARGET TERMINATION RECEIVED BY PI7C7300A ....................................................... 36
4.9.3.1 4.9.3.2 4.9.3.3 DELAYED WRITE TARGET TERMINATION RESPONSE........................................................ 36 POSTED WRITE TARGET TERMINATION RESPONSE ........................................................... 37 DELAYED READ TARGET TERMINATION RESPONSE ......................................................... 38
4.9.4
4.9.4.1 4.9.4.2 4.9.4.3
TARGET TERMINATION INITIATED BY PI7C7300A ....................................................... 38
TARGET RETRY............................................................................................................................ 38 TARGET DISCONNECT................................................................................................................ 39 TARGET ABORT ........................................................................................................................... 40
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 4.10 5 CONCURRENT MODE OPERATION ....................................................................................... 40
ADDRESS DECODING .................................................................................................................... 40 5.1 ADDRESS RANGES ................................................................................................................... 40 5.2 I/O ADDRESS DECODING ........................................................................................................ 41 5.2.1 I/O BASE AND LIMIT ADDRESS REGISTER..................................................................... 42 5.2.2 ISA MODE............................................................................................................................ 42 5.3 MEMORY ADDRESS DECODING............................................................................................ 43 5.3.1 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ................................ 43 5.3.2 PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ......................... 44 5.4 VGA SUPPORT ........................................................................................................................... 45 5.4.1 VGA MODE.......................................................................................................................... 45 5.4.2 VGA SNOOP MODE ............................................................................................................ 46
6
TRANSACTION ORDERING.......................................................................................................... 46 6.1 6.2 6.3 6.4 TRANSACTIONS GOVERNED BY ORDERING RULES........................................................ 46 GENERAL ORDERING GUIDELINES...................................................................................... 47 ORDERING RULES .................................................................................................................... 48 DATA SYNCHRONIZATION .................................................................................................... 49
7
ERROR HANDLING......................................................................................................................... 50 7.1 ADDRESS PARITY ERRORS .................................................................................................... 50 7.2 DATA PARITY ERRORS ........................................................................................................... 51 7.2.1 CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE ................. 51 7.2.2 READ TRANSACTIONS ....................................................................................................... 51 7.2.3 DELAYED WRITE TRANSACTIONS ................................................................................... 52 7.2.4 POSTED WRITE TRANSACTIONS...................................................................................... 55 7.3 DATA PARITY ERROR REPORTING SUMMARY ................................................................. 56 7.4 SYSTEM ERROR (SERR#) REPORTING.................................................................................. 60
8
EXCLUSIVE ACCESS...................................................................................................................... 61 8.1 CONCURRENT LOCKS ............................................................................................................. 61 8.2 ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C7300A..................................................... 61 8.2.1 LOCKED TRANSACTIONS IN DOWSTREAM DIRECTION.............................................. 61 8.2.2 LOCKED TRANSACTION IN UPSTREAM DIRECTION.................................................... 63 8.3 ENDING EXCLUSIVE ACCESS ................................................................................................ 63
9
PCI BUS ARBITRATION................................................................................................................. 64 9.1 PRIMARY PCI BUS ARBITRATION......................................................................................... 64 9.2 SECONDARY PCI BUS ARBITRATION .................................................................................. 64 9.2.1 SECONDARY BUSARBITRATION USING THE INTERNAL ARBITER ............................. 64 9.2.2 PREEMPTION ..................................................................................................................... 66 9.2.3 SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER.............................. 66 9.2.4 BUS PARKING..................................................................................................................... 66
10 11 11.1 11.2 12 12.1 12.2
COMPACT PCI HOT SWAP ....................................................................................................... 67 CLOCKS ......................................................................................................................................... 67 PRIMARY CLOCK INPUTS....................................................................................................... 67 SECONDARY CLOCK OUTPUTS............................................................................................. 67 RESET............................................................................................................................................. 68 PRIMARY INTERFACE RESET ................................................................................................ 68 SECONDARY INTERFACE RESET .......................................................................................... 68 Page 6 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 13 13.1 13.2 14 SUPPORTED COMMANDS ........................................................................................................ 69 PRIMARY INTERFACE ............................................................................................................. 69 SECONDARY INTERFACE ....................................................................................................... 70 CONFIGURATION REGISTERS ............................................................................................... 70
14.1 CONFIGURATION REGISTER 1 AND 2 .................................................................................. 72 14.1.1 VENDOR ID REGISTER - OFFSET 00h............................................................................. 72 14.1.2 DEVICE ID REGISTER - OFFSET 00h .............................................................................. 73 14.1.3 COMMAND REGISTER - OFFSET 04h ............................................................................. 73 14.1.4 STATUS REGISTER - OFFSET 04h.................................................................................... 74 14.1.5 REVISION ID REGISTER - OFFSET 08h........................................................................... 75 14.1.6 CLASS CODE REGISTER - OFFEST 08h .......................................................................... 75 14.1.7 CACHE LINE SIZE REGISTER - OFFSET 0Ch ................................................................. 75 14.1.8 PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch.................................................. 75 14.1.9 HEADER TYPE REGISTER - OFFSET 0Ch ....................................................................... 76 14.1.10 PRIMARY BUS NUMBER REGISTER - OFFSET 18h ................................................... 76 14.1.11 SECONDARY (S1 or S2) BUS NUMBER REGISTER - OFFSET 18h ............................ 76 14.1.12 SUBORDINATE (S1 or S2) BUS NUMBER REGISTER - OFFSET 18h ........................ 76 14.1.13 SECONDARY LATENCY TIMER REGISTER - OFFSET 18h ........................................ 76 14.1.14 I/O BASE REGISTER - OFFSET 1Ch ............................................................................. 77 14.1.15 I/O LIMIT REGISTER - OFFSET 1Ch ............................................................................ 77 14.1.16 SECONDARY STATUS REGISTER - OFFSET 1Ch........................................................ 77 14.1.17 MEMORY BASE REGISTER - OFFSET 20h................................................................... 78 14.1.18 MEMORY LIMIT REGISTER - OFFSET 20h.................................................................. 78 14.1.19 PREFETCHABLE MEMORY BASE REGISTER - OFFSET 24h .................................... 78 14.1.20 PREFETCHABLE MEMORY LIMIT REGISTER - OFFSET 24h ................................... 79 14.1.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER - OFFSET 28h .......................................................................................................................................... 79 14.1.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER - OFFSET 2Ch .......................................................................................................................................... 79 14.1.23 I/O BASE ADDRESS UPPER 16-BITS REGISTER - Offset 30h..................................... 79 14.1.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER - OFFSET 30h............................... 80 14.1.25 ECP POINTER REGISTER - OFFSET 34h..................................................................... 80 14.1.26 BRIDGE CONTROL REGISTER - OFFSET 3Ch............................................................ 80 14.1.27 DIAGNOSTIC / CHIP CONTROL REGISTER - OFFSET 40h ....................................... 81 14.1.28 ARBITER CONTROL REGISTER - OFFSET 40h........................................................... 83 14.1.29 UPSTREAM MEMORY CONTROL REGISTER - OFFSET 48h..................................... 83 14.1.30 HOT SWAP SWITCH TIME SLOT REGISTER - OFFSET 4Ch...................................... 83 14.1.31 UPSTREAM (S1 or S2 to P) MEMORY BASE REGISTER - OFFSET 50h..................... 84 14.1.32 UPSTREAM (S1 or S2 to P) MEMORY LIMIT REGISTER - OFFSET 50h.................... 84 14.1.33 UPSTREAM (S1 or S2 to P) MEMORY BASE UPPER 32-BITS REGISTER - OFFSET 54h .......................................................................................................................................... 84 14.1.34 UPSTREAM (S1 or S2 to P) MEMORY LIMIT UPPER 32 BITS REGISTER - OFFSET 58h .......................................................................................................................................... 85 14.1.35 P_SERR# EVENT DISABLE REGISTER - OFFSET 64h ................................................ 85 14.1.36 SECONDARY CLOCK CONTROL REGISTER - OFFSET 68h ...................................... 86 14.1.37 PORT OPTION REGISTER - OFFSET 74h .................................................................... 86 14.1.38 MASTER TIMEOUT COUNTER REGISTER - OFFSET 74h ......................................... 88 14.1.39 RETRY COUNTER REGISTER - OFFSET 78h............................................................... 88 14.1.40 SAMPLING TIMER REGISTER - OFFSET 7Ch............................................................. 88 14.1.41 SECONDARY SUCCESSFUL I/O READ COUNTER REGISTER - OFFSET 80h ......... 88 14.1.42 SECONDARY SUCCESSFUL I/O WRITE COUNTER REGISTER - OFFSET 84h........ 89 14.1.43 SECONDARY SUCCESSFUL MEMORY READ COUNTER REGISTER - Offset 88h.. 89 Page 7 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 14.1.44 14.1.45 14.1.46 14.1.47 14.1.48 14.1.49 14.1.50 14.1.51 14.1.52 14.1.53 14.1.54 14.1.55 15 SECONDARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER - OFFSET 8Ch .......................................................................................................................................... 89 PRIMARY SUCCESSFUL I/O READ COUNTER REGISTER - OFFSET 90h ............... 89 PRIMARY SUCCESSFUL I/O WRITE COUNTER REGISTER - OFFSET 94h.............. 89 PRIMARY SUCCESSFUL MEMORY READ COUNTER REGISTER - OFFSET 98h .... 90 PRIMARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER - OFFSET 9Ch.. 90 CAPABILITY ID REGISTER - OFFSET B0h .................................................................. 90 NEXT POINTER REGISTER - OFFSET B0h .................................................................. 90 SLOT NUMBER REGISTER - OFFSET B0h................................................................... 91 CHASSIS NUMBER REGISTER - OFFSET B0h............................................................. 91 CAPABILITY ID REGISTER - OFFSET C0h .................................................................. 91 NEXT POINTER REGISTER - OFFSET C0h.................................................................. 91 HOT SWAP CONTROL AND STATUS REGISTER - OFFSET C0h ............................... 91
BRIDGE BEHAVIOR.................................................................................................................... 92
15.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES ............................................................... 92 15.2 TRANSACTION ORDERING .................................................................................................... 93 15.3 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)..................................... 93 15.3.1 MASTER ABORT.................................................................................................................. 93 15.3.2 PARITY AND ERROR REPORTING.................................................................................... 93 15.3.3 REPORTING PARITY ERRORS........................................................................................... 94 15.3.4 SECONDARY IDSEL MAPPING ......................................................................................... 94 16 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ............................................................... 94 16.1 BOUNDARY SCAN ARCHITECTURE..................................................................................... 95 16.1.1 TAP PINS.............................................................................................................................. 95 16.1.2 INSTRUCTION REGISTER.................................................................................................. 95 16.2 BOUNDARY-SCAN INSTRUCTION SET ................................................................................ 96 16.3 TAP TEST DATA REGISTERS .................................................................................................. 97 16.4 BYPASS REGISTER ................................................................................................................... 97 16.5 BOUNDARY-SCAN REGISTER................................................................................................ 97 16.6 TAP CONTROLLER ................................................................................................................... 97 17 17.1 17.2 17.3 17.4 17.5 17.6 18 18.1 ELECTRICAL AND TIMING SPECIFICATIONS................................................................. 100 MAXIMUM RATINGS ............................................................................................................. 101 3.3V DC SPECIFICATIONS ..................................................................................................... 101 3.3V AC SPECIFICATIONS ..................................................................................................... 102 PRIMARY AND SECONDARY BUSES AT 66MHZ CLOCK TIMING ................................. 103 PRIMARY AND SECONDARY BUSES AT 33MHZ CLOCK TIMING ................................. 103 POWER CONSUMPTION ........................................................................................................ 103 272-PIN PBGA PACKAGE FIGURE ........................................................................................ 104 PART NUMBER ORDERING INFORMATION ...................................................................... 104
APPENDIX A: PI7C7300A EVALUATION BOARD USER'S MANUAL....................................... 105 FREQUENTLY ASKED QUESTIONS ................................................................................................. 107
LIST OF TABLES
TABLE 4-1 TABLE 4-2 TABLE 4-3 TABLE 4-4 PCI TRANSACTIONS .............................................................................................................. 21 WRITE TRANSACTION FORWARDING .............................................................................. 23 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES................................... 26 READ PREFETCH ADDRESS BOUNDARIES....................................................................... 27 Page 8 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION TABLE 4-5 READ TRANSACTION PREFETCHING ................................................................................ 28 TABLE 4-6 DEVICE NUMBER TO IDSEL S1_AD OR S2_AD PIN MAPPING ....................................... 32 TABLE 4-7 DELAYED WRITE TARGET TERMINATION RESPONSE.................................................. 37 TABLE 4-8 RESPONSE TO POSTED WRITE TARGET TERMINATION ............................................... 37 TABLE 4-9 RESPONSE TO DELAYED READ TARGET TERMINATION ............................................. 38 TABLE 6-1 SUMMARY OF TRANSACTION ORDERING....................................................................... 48 TABLE 7-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT ....................... 56 TABLE 7-2 SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT ......................... 57 TABLE 7-3 SETTING PRIMARY INTERFACE DATA PARITY ERROR DETECTED BIT.................... 57 TABLE 7-4 SETTING SECONDARY INTERFACE DATA PARITY ERROR DETECTED BIT ............. 58 TABLE 7-5 ASSERTION OF P_PERR#....................................................................................................... 58 TABLE 7-6 ASSERTION OF S_PERR#....................................................................................................... 59 TABLE 7-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS ................................................... 59 TABLE 16-1 TAP PINS ................................................................................................................................ 96 TABLE 16-2 JTAG BOUNDARY REGISTER ORDER .............................................................................. 98
LIST OF FIGURES
FIGURE 9-1 SECONDARY ARBITER EXAMPLE..................................................................................... 65 FIGURE 16-1 TEST ACCESS PORT BLOCK DIAGRAM.......................................................................... 95 FIGURE 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS ................................................. 102 FIGURE 18-1 272-PIN PBGA PACKAGE ................................................................................................. 104
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
1
INTRODUCTION
PRODUCT DESCRIPTION
The PI7C7300A is Pericom Semiconductor's second-generation PCI-PCI Bridge. It is designed to be fully compliant with the 32-bit, 66MHz implementation of the PCI Local Bus Specification, Revision 2.2. The PI7C7300A supports only synchronous bus transactions between devices on the Primary Bus running at 33MHz to 66MHz and the Secondary Buses operating at either 33MHz or 66MHz. The Primary and Secondary Buses can also operate in concurrent mode, resulting in added increase in system performance. Concurrent bus operation off-loads and isolates unnecessary traffic from the Primary Bus; thereby enabling a master and a target device on the same Secondary PCI Bus to communicate even while the Primary Bus is busy. In addition, the Secondary Buses have load balancing capability, allowing faster devices to be isolated away from slower devices. Among the other features supported by the PI7C7300A are: support for up to 15 devices on the Secondary Buses, Compact PCI Hot Swap (PICMG 2.1, R1.0) Friendly Support and Dual Addressing Cycle.
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PRODUCT FEATURES
32-bit Primary and Two Secondary Ports run up to 66MHz All 3 ports compliant with the PCI Local Bus Specification, Revision 2.2 Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1. - All I/O and memory commands - Type 1 to Type 0 configuration conversion - Type 1 to Type 1 configuration forwarding - Type 1 configuration write to special cycle conversion Concurrent Primary to Secondary Bus operation and independent intra-Secondary Port channel to reduce traffic on the Primary Port Provides internal arbitration for one set of eight secondary bus masters (S1 bus) and one set of seven (eight if Hot Swap is disable)secondary bus masters (S2 bus) - Programmable 2-level priority arbiter - Disable control for use of external arbiter Supports posted write buffers in all directions Three 128 byte FIFO's for delay transactions Three 128 byte FIFO's for posted memory transactions Enhanced address decoding - 32-bit I/O address range - 32-bit memory-mapped I/O address range - VGA addressing and VGA palette snooping - ISA-aware mode for legacy support in the first 64KB of I/O address range Dual Addressing cycle (64-bit) Interrupt handling - PCI interrupts are routed through an external interrupt concentrator Supports system transaction ordering rules Tri-state control of output buffers on secondary buses Compact PCI Hot Swap (PICMG 2.1, R1.0) Friendly Support Industrial Temperature range -40C to 85C IEEE 1149.1 JTAG interface support 3.3V core; 3.3V PCI I/O interface with 5V I/O tolerance 272-pin plastic BGA package
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2
BLOCK DIAGRAM
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
3
3.1
SIGNAL DEFINITIONS
SIGNAL TYPES
Signal Type PI PIU PID PO PB PSTS Description PCI input (3.3V, 5V tolerant) PCI input (3.3V, 5V tolerant) with weak pull-up PCI input (3.3V, 5V tolerant) with weak pull-down PCI output (3.3V) PCI tri-state bidirectional (3.3V, 5V tolerant) PCI sustained tri-state bi-directional (Active LOW signal which must be driven inactive for one cycle before being tri-stated to ensure HIGH performance on a shared signal line) PCI tri-state output PCI output which either drives LOW (active state) or tri-state
PTS POD
3.2
PRIMARY BUS INTERFACE SIGNALS
Name P_AD[31:0] Pin # Y7, W7, Y8, W8, V8, U8, Y9, W9, W10, V10, Y11, V11, U11, Y12, W12, V12, V16, W16, Y16, W17, Y17, U18, W18, Y18, U19, W19, Y19, U20, V20, Y20, T17, R17 V9, U12, U16, V19 Type PB Description Primary Address/Data. Multiplexed address and data bus. Address is indicated by P_FRAME# assertion. Write data is stable and valid when P_IRDY# is asserted and read data is stable and valid when P_TRDY# is asserted. Data is transferred on rising clock edges when both P_IRDY# and P_TRDY# are asserted. During bus idle, PI7C7300A drives P_AD to a valid logic level when P_GNT# is asserted.
P_CBE[3:0]
PB
P_PAR
U15
PB
P_FRAME#
W13
PSTS
Primary Command/Byte Enables. Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. The initiator then drives the byte enables during data phases. During bus idle, PI7C7300A drives P_CBE[3:0] to a valid logic level when P_GNT# is asserted. Primary Parity. Parity is even across P_AD[31:0], P_CBE[3:0], and P_PAR (i.e. an even number of 1's). P_PAR is an input and is valid and stable one cycle after the address phase (indicated by assertion of P_FRAME#) for address parity. For write data phases, P_PAR is an input and is valid one clock after P_IRDY# is asserted. For read data phase, P_PAR is an output and is valid one clock after P_TRDY# is asserted. Signal P_PAR is tri-stated one cycle after the P_AD lines are tri-stated. During bus idle, PI7C7300A drives P_PAR to a valid logic level when P_GNT# is asserted. Primary FRAME (Active LOW). Driven by the initiator of a transaction to indicate the beginning and duration of an access. The de-assertion of P_FRAME# indicates the final data phase requested by the initiator. Before being tri-stated, it is driven to a de-asserted state for one cycle.
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Name P_IRDY# Pin # V13 Type PSTS Description Primary IRDY (Active LOW). Driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary TRDY (Active LOW). Driven by the target of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary Device Select (Active LOW). Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C7300A waits for the assertion of this signal within 5 cycles of P_FRAME# assertion; otherwise, terminate with master abort. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary STOP (Active LOW). Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary LOCK (Active LOW). Asserted by the master for multiple transactions to complete. Primary ID Select. Used as a chip select line for Type 0 configuration accesses to PI7C7300A configuration space. Primary Parity Error (Active LOW). Asserted when a data parity error is detected for data received on the primary interface. Before being tri-stated, it is driven to a de-asserted state for one cycle. Primary System Error (Active LOW). Can be driven LOW by any device to indicate a system error condition. PI7C7300A drives this pin on: ! Address parity error ! Posted write data parity error on target bus ! Secondary S1_SERR# or S2_SERR# asserted ! Master abort during posted write transaction ! Target abort during posted write transaction ! Posted write transaction discarded ! Delayed write request discarded ! Delayed read request discarded ! Delayed transaction master timeout This signal requires an external pull-up resistor for proper operation. Primary Request (Active LOW). This is asserted by PI7C7300A to indicate that it wants to start a transaction on the primary bus. PI7C7300A de-asserts this pin for at least 2 PCI clock cycles before asserting it again. Primary Grant (Active LOW). When asserted, PI7C7300A can access the primary bus. During idle and P_GNT# asserted, PI7C7300A will drive P_AD, P_CBE, and P_PAR to valid logic levels. Primary RESET (Active LOW). When P_RESET# is active, all PCI signals should be asynchronously tri-stated.
P_TRDY#
U13
PSTS
P_DEVSEL#
Y14
PSTS
P_STOP#
W14
PSTS
P_LOCK# P_IDSEL
V14 Y10
PSTS PI
P_PERR#
Y15
PSTS
P_SERR#
W15
POD
P_REQ#
W6
PTS
P_GNT#
U7
PI
P_RESET#
Y5
PI
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name P_M66EN Pin # V18 Type PI Description Primary Interface 66MHz Operation. This input is used to specify if PI7C7300A is capable of running at 66MHz. For 66MHz operation on the Primary bus, this signal should be pulled "HIGH". For 33MHz operation on the Primary bus, this signal should be pulled "LOW". In this condition, S1_M66EN and S2_M66EN will both need to be "LOW", forcing both secondary buses to run at 33MHz also.
3.3
SECONDARY BUS INTERFACE SIGNALS
Name S1_AD[31:0], Pin # B20, B19, C20, C19, C18, D20, D19, D17, E19, E18, E17, F20, F19, F17, G20, G19, L20, L19, L18, M20, M19, M17, N20, N19, N18, N17, P17, R20, R19, R18, T20, T19 J4, H1, H2, H3, H4, G1, G3, G4, F2, F3, F4, E1, E4, D1, C1, B1, C5, B5, D6, C6, B6, A6, C7, B7, D8, C8, D9, C9, B9, A9, D10, C10 E20, G18, K17, P20 F1, A1, A4, A7 Type PB Description Secondary Address/Data. Multiplexed address and data bus. Address is indicated by S1_FRAME# or S2_FRAME# assertion. Write data is stable and valid when S1_IRDY# or S2_IRDY# is asserted and read data is stable and valid when S1_IRDY# or S2_IRDY# is asserted. Data is transferred on rising clock edges when both S1_IRDY# or S2_IRDY# and S1_TRDY# or S2_TRDY# are asserted. During bus idle, PI7C7300A drives S1_AD or S2_AD to a valid logic level when S1_GNT# or S2_GNT# is asserted respectively.
S2_AD[31:0]
S1_CBE[3:0], S2_CBE[3:0]
PB
S1_PAR, S2_PAR
K18, B4
PB
S1_FRAME#, S2_FRAME#
H20, D2
PSTS
Secondary Command/Byte Enables. Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. The initiator then drives the byte enables during data phases. During bus idle, PI7C7300A drives S1_CBE[3:0] or S2_CBE[3:0] to a valid logic level when the internal grant is asserted. Secondary Parity. Parity is even across S1_AD[31:0], S1_CBE[3:0], and S1_PAR or S2_AD[31:0], S2_CBE[3:0], and S2_PAR (i.e. an even number of 1's). S1_PAR or S2_PAR is an input and is valid and stable one cycle after the address phase (indicated by assertion of S1_FRAME# or S2_FRAME#) for address parity. For write data phases, S1_PAR or S2_PAR is an input and is valid one clock after S1_IRDY# S2_IRDY# is asserted. For read data phase, S1_PAR or S2_PAR is an output and is valid one clock after S1_TRDY# or S2_TRDY# is asserted. Signal S1_PAR or S2_PAR is tri-stated one cycle after the S1_AD or S2_AD lines are tri-stated. During bus idle, PI7C7300A drives S1_PAR or S2_PAR to a valid logic level when the internal grant is asserted. Secondary FRAME (Active LOW). Driven by the initiator of a transaction to indicate the beginning and duration of an access. The de-assertion of S1_FRAME# or S2_FRAME# indicates the final data phase requested by the initiator. Before being tristated, it is driven to a de-asserted state for one cycle.
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Name S1_IRDY#, S2_IRDY# Pin # H19, B2 Type PSTS Description Secondary IRDY (Active LOW). Driven by the initiator of a transaction to indicate its ability to complete current data phase on the secondary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Secondary TRDY (Active LOW). Driven by the target of a transaction to indicate its ability to complete current data phase on the secondary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Secondary Device Select (Active LOW). Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C7300A waits for the assertion of this signal within 5 cycles of S1_FRAME# or S2_FRAME# assertion; otherwise, terminate with master abort. Before tri-stated, it is driven to a deasserted state for one cycle. Secondary STOP (Active LOW). Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tristated, it is driven to a de-asserted state for one cycle. Secondary LOCK (Active LOW). Asserted by the master for multiple transactions to complete. Secondary Parity Error (Active LOW). Asserted when a data parity error is detected for data received on the secondary interface. Before being tri-stated, it is driven to a de-asserted state for one cycle. Secondary System Error (Active LOW). Can be driven LOW by any device to indicate a system error condition. Secondary Request (Active LOW). This is asserted by an external device to indicate that it wants to start a transaction on the secondary bus. The input is externally pulled up through a resistor to VDD. Secondary Grant (Active LOW). PI7C7300A asserts this pin to access the secondary bus. PI7C7300A deasserts this pin for at least 2 PCI clock cycles before asserting it again. During idle and S1_GNT# or S2GNT# asserted, PI7C7300A will drive S1_AD, S1_CBE, and S1_PAR or S2_AD, S2_CBE, and S2_PAR. Secondary RESET (Active LOW). Asserted when any of the following conditions are met: 1. Signal P_RESET# is asserted. 2. Secondary reset bit in bridge control register in configuration space is set. When asserted, all control signals are tri-stated and zeroes are driven on S1_AD, S1_CBE, and S1_PAR or S2_AD, S2_CBE, and S2_PAR. Secondary Enable (Active HIGH). When S1_EN or S2_EN is inactive, secondary bus PCI S1 or PCI S2 will be asynchronously tri-stated. Secondary Interface 66MHz Operation. This input is used to specify if PI7C7300A is capable of running at 66MHz on the secondary side. When HIGH, the S1 or S2 bus may run at 66MHz. When LOW, the S1 or S2 bus may only run at 33MHz. If P_M66EN is pulled LOW, both S1_M66EN and S2_M66EN need to be LOW.
S1_TRDY#, S2_TRDY#
H18, A2
PSTS
S1_DEVSEL#, S2_DEVSEL#
J20, D3
PSTS
S1_STOP#, S2_STOP#
J19, C3
PSTS
S1_LOCK#, S2_LOCK# S1_PERR#, S2_PERR#
J18, B3 J17, D4
PSTS PSTS
S1_SERR#, S2_SERR# S1_REQ#[7:0], S2_REQ#[6:0] S1_GNT#[7:0] S2_GNT#[6:0]
K20, C4 B11, A12, D13, C13, C15, A16, C17, B17 R3, P2, P1, M2, M1, K1, K3 C11, B12, B13, A14, D14, B16, D16, B18 P4, R1, N4, M3, L4, L1, K2
PI
PIU
PO
S1_RESET#, S2_RESET#
B10, T4
PO
S1_EN, S2_EN S1_M66EN, S2_M66EN
W3, W4 D7, W5
PIU
PI
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name S_CFN# Pin # Y2 Type PIU Description Secondary Bus Central Function Control Pin. When tied LOW, it enables the internal arbiter. When tied HIGH, an external arbiter must be used. S1_REQ#[0] or S2_REQ#[0] is reconfigured to be the secondary bus grant input, and S1_GNT#[0] or S2_GNT#[0] is reconfigured to be the secondary bus request output.
3.4
CLOCK SIGNALS
Name P_CLK S1_CLKOUT [7:0] S2_CLKOUT [7:0] Pin # V6 A11, C12, A13, B14, B15, C16, A18, A19 T3, T1, P3, N3, M4, L3, L2, J1 Type PI PTS Description Primary Clock Input. Provides timing for all transactions on the primary interface. Secondary Clock Output. Provides secondary 1 clocks phase synchronous with the P_CLK. Secondary Clock Output. Provides secondary 2 clocks phase synchronous with the P_CLK.
PTS
3.5
MISCELLANEOUS SIGNALS
Name BYPASS PLL_TM S_CLKIN SCAN_TM# Pin # Y4 Y3 V5 V4 Type PI PI PI PI Description Reserved. Reserved for future use. Must be tied HIGH. Reserved. Reserved for future use. Must be tied LOW. Reserved. Reserved for future use. Must be tied LOW. Full-Scan Test Mode Enable (Active LOW). Connect HIGH for normal operation. When SCAN_TM# is active, the ten scan chains will be enabled. The scan clock is P_CLK. The scan input and outputs are as follows: S1_REQ[6], S1_REQ[5], S1_REQ[4], S1_REQ[3], S1_REQ[2], S2_REQ#[6], S2_REQ#[5], S2_REQ#[4], S2_REQ#[3], S2_REQ#[2], and S1_GNT#[6], S1_GNT#[5], S1_GNT#[4], S1_GNT#[3], S1_GNT#[2], S2_GNT#[6], S2_GNT#[5], S2_GNT#[4], S2_GNT#[3], S2_GNT#[2] Full-Scan Enable Control. SCAN_EN should be tied LOW in normal mode. When SCAN_EN is LOW, fullscan is in shift operation if SCAN_TM# is active. When SCAN_EN is HIGH, full-scan is in parallel operation if SCAN_TM# is active.
SCAN_EN
U5
PID
3.6
COMPACT PCI HOT-SWAP SIGNALS
Name LOO Pin # U1 Type PO Description Hot Swap LED. The output of this pin lights a blue LED to indicate insertion and removal ready status. If HS_EN is LOW, pin is S2_GNT#[7]. Hot Swap Switch. When driven LOW, this signal indicates that the board ejector handle indicates an insertion or impending extraction of a board. If HS_EN is LOW, pin is S2_REQ#[7]. Hot Swap Enable. To enable Hot Swap Friendly support, this signal should be pulled HIGH.
HS_SW#
T2
PI
HS_EN
U6
PI
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name ENUM# Pin # R4 Type POD Description Hot Swap Status Indicator. The output of ENUM# indicates to the system that an insertion has occurred of that an extraction is about to occur.
3.7
JTAG BOUNDARY SCAN SIGNALS
Name TCK TMS TDO Pin # V2 W1 V3 Type PIU PIU PTS Description Test Clock. Used to clock state information and data into and out of the PI7C7300A during boundary scan. Test Mode Select. Used to control the state of the Test Access Port controller. Test Data Output. When SCAN_EN is HIGH, it is used (in conjunction with TCK) to shift data out of the Test Access Port (TAP) in a serial bit stream. Test Data Input. When SCAN_EN is HIGH, it is used (in conjunction with TCK) to shift data and instructions into the Test Access Port (TAP) in a serial bit stream. Test Reset. Active LOW signal to reset the Test Access Port (TAP) controller into an initialized state.
TDI
W2
PIU
TRST#
U3
PIU
3.8
POWER AND GROUND
Name VDD Pin # B8, C14, D5, D11, D15, E2, F18, J3, L17, N2, P19, U10, V1, V7, V15, W20 A3, A5, A8, A10, A15, A17, A20, C2, D12, D18, E3, G2, G17, H17, J2, J9, J10, J11, J12, K4, K9, K10, K11, K12, K19, L9, L10, L11, L12, M9, M10, M11, M12, M18, N1, P18, R2, T18, U2, U9, U14, U17, V17, W11, Y6, Y13 Y1 U4 Type Description 3.3V Digital Power
VSS
Digital Ground
AVCC AGND
Analog 3.3V for PLL Analog Ground for PLL
3.9
PI7C7300A PBGA PIN LIST
Pin # A1 A3 A5 A7 A9 A11 A13 A15 Name S2_CBE[2] VSS VSS S2_CBE[0] S2_AD[2] S1_CLKOUT[7] S1_CLKOUT[5] VSS Type PB PB PB PTS PTS Pin # A2 A4 A6 A8 A10 A12 A14 A16 Name S2_TRDY# S2_CBE[1] S2_AD[10] VSS VSS S1_REQ#[6] S1_GNT#[4] S1_REQ#[2] Type PSTS PB PB PIU PO PIU
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Pin # A17 A19 B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 C1 C3 C5 C7 C9 C11 C13 C15 C17 C19 D1 D3 D5 D7 D9 D11 D13 D15 D17 D19 E1 E3 E17 E19 F1 F3 F17 F19 G1 G3 G17 G19 H1 H3 H17 H19 J1 J3 J9 J11 J17 J19 K1 K3 K9 K11 K17 K19 L1 L3 L9 Name VSS S1_CLKOUT[0] S2_AD[16] S2_LOCK# S2_AD[14] S2_AD[8] S2_AD[3] S1_REQ#[7] S1_GNT#[5] S1_CLKOUT[3] S1_REQ#[0] S1_AD[30] S2_AD[17] S2_STOP# S2_AD[15] S2_AD[9] S2_AD[4] S1_GNT#[7] S1_REQ#[4] S1_REQ#[3] S1_REQ#[1] S1_AD[28] S2_AD[18] S2_DEVSEL# VDD S1_M66EN S2_AD[5] VDD S1_REQ#[5] VDD S1_AD[24] S1_AD[25] S2_AD[20] VSS S1_AD[21] S1_AD[23] S2_CBE[3] S2_AD[22] S1_AD[18] S1_AD[19] S2_AD[26] S2_AD[25] VSS S1_AD[16] S2_AD[30] S2_AD[28] VSS S1_IRDY# S2_CLKOUT[0] VDD VSS VSS S1_PERR# S1_STOP# S2_REQ#[1] S2_REQ#[0] VSS VSS S1_CBE[1] VSS S2_GNT#[1] S2_CLKOUT[2] VSS Type PTS PB PSTS PB PB PB PIU PO PTS PIU PB PB PSTS PB PB PB PO PIU PIU PIU PB PB PSTS PI PB PIU PB PB PB PB PB PB PB PB PB PB PB PB PB PB PSTS PTS PSTS PSTS PIU PIU PB PO PTS Pin # A18 A20 B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 C2 C4 C6 C8 C10 C12 C14 C16 C18 C20 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 E2 E4 E18 E20 F2 F4 F18 F20 G2 G4 G18 G20 H2 H4 H18 H20 J2 J4 J10 J12 J18 J20 K2 K4 K10 K12 K18 K20 L2 L4 L10 Name S1_CLKOUT[1] VSS S2_IRDY# S2_PAR S2_AD[11] VDD S1_RESET# S1_GNT#[6] S1_CLKOUT[4] S1_GNT#[2] S1_GNT#[0] S1_AD[31] VSS S2_SERR# S2_AD[12] S2_AD[6] S2_AD[0] S1_CLKOUT[6] VDD S1_CLKOUT[2] S1_AD[27] S1_AD[29] S2_FRAME# S2_PERR# S2_AD[13] S2_AD[7] S2_AD[1] VSS S1_GNT#[3] S1_GNT#[1] VSS S1_AD[26] VDD S2_AD[19] S1_AD[22] S1_CBE[3] S2_AD[23] S2_AD[21] VDD S1_AD[20] VSS S2_AD[24] S1_CBE[2] S1_AD[17] S2_AD[29] S2_AD[27] S1_TRDY# S1_FRAME# VSS S2_AD[31] VSS VSS S1_LOCK# S1_DEVSEL# S2_GNT#[0] VSS VSS VSS S1_PAR S1_SERR# S2_CLKOUT[1] S2_GNT#[2] VSS Type PTS PSTS PB PB PO PO PTS PO PO PB PI PB PB PB PTS PTS PTS PB PB PSTS PSTS PB PB PB PO PO PB PB PB PB PB PB PB PB PB PB PB PB PSTS PSTS PB PSTS PSTS PO PB PI PTS PO -
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Pin # L11 L17 L19 M1 M3 M9 M11 M17 M19 N1 N3 N17 N19 P1 P3 P17 P19 R1 R3 R17 R19 T1 T3 T17 T19 U1 U3 U5 U7 U9 U11 U13 U15 U17 U19 V1 V3 V5 V7 V9 V11 V13 V15 V17 V19 W1 W3 W5 W7 W9 W11 W13 W15 W17 W19 Y1 Y3 Y5 Y7 Y9 Y11 Y13 Y15 Name VSS VDD S1_AD[14] S2_REQ#[2] S2_GNT#[3] VSS VSS S1_AD[10] S1_AD[11] VSS S2_CLKOUT[4] S1_AD[6] S1_AD[8] S2_REQ#[4] S2_CLKOUT[5] S1_AD[5] VDD S2_GNT#[5] S2_REQ#[6] P_AD[0] S1_AD[3] S2_CLKOUT[6] S2_CLKOUT[7] P_AD[1] S1_AD[0] LOO TRST# SCAN_EN P_GNT# VSS P_AD[19] P_TRDY# P_PAR VSS P_AD[7] VDD TDO S_CLKIN VDD P_CBE[3] P_AD[20] P_IRDY# VDD VSS P_CBE[0] TMS S1_EN S2_M66EN P_AD[30] P_AD[24] VSS P_FRAME# P_SERR# P_AD[12] P_AD[6] AVCC PLL_TM P_RESET# P_AD[31] P_AD[25] P_AD[21] VSS P_PERR# Type PB PIU PO PB PB PTS PB PB PIU PTS PB PO PIU PB PB PTS PTS PB PB PO PIU PID PI PB PB PB PB PTS PI PB PB PB PB PIU PIU PI PB PB PB POD PB PB PI PI PB PB PB PSTS Pin # L12 L18 L20 M2 M4 M10 M12 M18 M20 N2 N4 N18 N20 P2 P4 P18 P20 R2 R4 R18 R20 T2 T4 T18 T20 U2 U4 U6 U8 U10 U12 U14 U16 U18 U20 V2 V4 V6 V8 V10 V12 V14 V16 V18 V20 W2 W4 W6 W8 W10 W12 W14 W16 W18 W20 Y2 Y4 Y6 Y8 Y10 Y12 Y14 Y16 Name VSS S1_AD[13] S1_AD[15] S2_REQ#[3] S2_CLKOUT[3] VSS VSS VSS S1_AD[12] VDD S2_GNT#[4] S1_AD[7] S1_AD[9] S2_REQ#[5] S2_GNT#[6] VSS S1_CBE[0] VSS ENUM# S1_AD[2] S1_AD[4] HS_SW S2_RESET# VSS S1_AD[1] VSS AGND HS_EN P_AD[26] VDD P_CBE[2] VSS P_CBE[1] P_AD[10] P_AD[4] TCK SCAN_TM# P_CLK P_AD[27] P_AD[22] P_AD[16] P_LOCK# P_AD[15] P_M66EN# P_AD[3] TDI S2_EN P_REQ# P_AD[28] P_AD[23] P_AD[17] P_STOP# P_AD[14] P_AD[9] VDD S_CFN# BYPASS VSS P_AD[29] P_IDSEL P_AD[18] P_DEVSEL# P_AD[13] Type PB PB PIU PTS PB PO PB PB PIU PO PB POD PB PB PI PO PB PI PB PB PB PB PB PIU PI PI PB PB PB PSTS PB PI PB PIU PIU PTS PB PB PB PSTS PB PB PIU PB PI PB PSTS PB
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Pin # Y17 Y19 Name P_AD[11] P_AD[5] Type PB PB Pin # Y18 Y20 Name P_AD[8] P_AD[2] Type PB PB
4
PCI BUS OPERATION
This Chapter offers information about PCI transactions, transaction forwarding across PI7C7300A, and transaction termination. The PI7C7300A has three 128-byte buffers for buffering of upstream and downstream transactions. These hold addresses, data, commands, and byte enables and are used for both read and write transactions.
4.1
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C7300A. Table 4-1 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when PI7C7300A initiates transactions as a master, on the primary (P) and secondary (S1, S2) buses, and when PI7C7300A responds to transactions as a target, on the primary (P) and secondary (S1, S2) buses. Table 4-1 PCI TRANSACTIONS
Types of Transactions 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate Initiates as Master Primary N Y Y Y N N Y Y N N N Y (Type 1 only) Y Y Y Y Secondary N Y Y Y N N Y Y N N Y Y Y Y Y Y Responds as Target Primary Secondary N N N N Y Y Y Y N N N N Y Y Y Y N N N N Y N Y Y (Type 1 only) Y Y Y Y Y Y Y Y
As indicated in Table 4-1, the following PCI commands are not supported by PI7C7300A: ! ! ! PI7C7300A never initiates a PCI transaction with a reserved command code and, as a target, PI7C7300A ignores reserved command codes. PI7C7300A does not generate interrupt acknowledge transactions. PI7C7300A ignores interrupt acknowledge transactions as a target. PI7C7300A does not respond to special cycle transactions. PI7C7300A cannot guarantee delivery of a special cycle transaction to downstream buses because of the Page 21 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION broadcast nature of the special cycle command and the inability to control the transaction as a target. To generate special cycle transactions on other PCI buses, either upstream or downstream, Type 1 configuration write must be used. PI7C7300A neither generates Type 0 configuration transactions on the primary PCI bus nor responds to Type 0 configuration transactions on the secondary PCI buses.
!
4.2
SINGLE ADDRESS PHASE
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and the bus command is driven on P_CBE[3:0]. PI7C7300A supports the linear increment address mode only, which is indicated when the lowest two address bits are equal to zero. If either of the lowest two address bits is nonzero, PI7C7300A automatically disconnects the transaction after the first data transfer.
4.3
DUAL ADDRESS PHASE
A 64-bit address uses two address phases. The first address phase is denoted by the asserting edge of FRAME#. The second address phase always follows on the next clock cycle. For a 32-bit interface, the first address phase contains dual address command code on the C/BE#[3:0] lines, and the low 32 address bits on the AD[31:0] lines. The second address phase consists of the specific memory transaction command code on the C/BE#[3:0] lines, and the high 32 address bits on the AD[31:0] lines. In this way, 64-bit addressing can be supported on 32-bit PCI buses. The PCI-to-PCI Bridge Architecture Specification supports the use of dual address transactions in the prefetchable memory range only. See Section 5.3.2 for a discussion of prefetchable address space. The PI7C7300A supports dual address transactions in both the upstream and the downstream direction. The PI7C7300A supports a programmable 64-bit address range in prefetchable memory for downstream forwarding of dual address transactions. Dual address transactions falling outside the prefetchable address range are forwarded upstream, but not downstream. Prefetching and posting are performed in a manner consistent with the guidelines given in this specification for each type of memory transaction in prefetchable memory space.
4.4
DEVICE SELECT (DEVSEL#) GENERATION
PI7C7300A always performs positive address decoding (medium decode) when accepting transactions on either the primary or secondary buses. PI7C7300A never does subtractive decode.
4.5
DATA PHASE
The address phase of a PCI transaction is followed by one or more data phases. A data phase is completed when IRDY# and either TRDY# or STOP# are asserted. Page 22 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION A transfer of data occurs only when both IRDY# and TRDY# are asserted during the same PCI clock cycle. The last data phase of a transaction is indicated when FRAME# is de-asserted and both TRDY# and IRDY# are asserted, or when IRDY# and STOP# are asserted. See Section 4.9 for further discussion of transaction termination. Depending on the command type, PI7C7300A can support multiple data phase PCI transactions. For detailed descriptions of how PI7C7300A imposes disconnect boundaries, see Section 4.6.4 for write address boundaries and Section 4.7.3 read address boundaries.
4.6
WRITE TRANSACTIONS
Write transactions are treated as either posted write or delayed write transactions. Table 4-2 shows the method of forwarding used for each type of write operation. Table 4-2 WRITE TRANSACTION FORWARDING
Type of Transaction Memory Write Memory Write and Invalidate Memory Write to VGA memory I/O Write Type 1 Configuration Write Type of Forwarding Posted (except VGA memory) Posted Delayed Delayed Delayed
4.6.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding is used for "Memory Write" and "Memory Write and Invalidate" transactions. When PI7C7300A determines that a memory write transaction is to be forwarded across the bridge, PI7C7300A asserts DEVSEL# with medium timing and TRDY# in the next cycle, provided that enough buffer space is available in the posted memory write queue for the address and at least one DWORD of data. Under this condition, PI7C7300A accepts write data without obtaining access to the target bus. The PI7C7300A can accept one DWORD of write data every PCI clock cycle. That is, no target wait state is inserted. The write data is stored in an internal posted write buffers and is subsequently delivered to the target. The PI7C7300A continues to accept write data until one of the following events occurs: ! ! ! The initiator terminates the transaction by de-asserting FRAME# and IRDY#. An internal write address boundary is reached, such as a cache line boundary or an aligned 4KB boundary, depending on the transaction type. The posted write data buffer fills up.
When one of the last two events occurs, the PI7C7300A returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. Once the posted write data moves to the head of the posted data queue, PI7C7300A asserts its request on the target bus. This can occur while PI7C7300A is still receiving data on the initiator bus. When the grant for the target bus is received and the target bus is detected in the idle condition, PI7C7300A asserts FRAME# and drives the stored write Page 23 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION address out on the target bus. On the following cycle, PI7C7300A drives the first DWORD of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. As long as write data exists in the queue, PI7C7300A can drive one DWORD of write data each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing through PI7C7300A and the initiator stalls, PI7C7300A will signal the last data phase for the current transaction at the target bus if the queue empties. PI7C7300A will restart the follow-on transactions if the queue has new data. PI7C7300A ends the transaction on the target bus when one of the following conditions is met: ! ! ! ! All posted write data has been delivered to the target. The target returns a target disconnect or target retry (PI7C7300A starts another transaction to deliver the rest of the write data). The target returns a target abort (PI7C7300A discards remaining write data). The master latency timer expires, and PI7C7300A no longer has the target bus grant (PI7C7300A starts another transaction to deliver remaining write data).
Section 4.9.3.2 provides detailed information about how PI7C7300A responds to target termination during posted write transactions.
4.6.2
MEMORY WRITE AND INVALIDATE TRANSACTIONS
Posted write forwarding is used for Memory Write and Invalidate transactions. The PI7C7300A disconnects Memory Write and Invalidate commands at aligned cache line boundaries. The cache line size value in the cache line size register gives the number of DWORD in a cache line. If the value in the cache line size register does meet the memory write and invalidate conditions, the PI7C7300A returns a target disconnect to the initiator either on a cache line boundary or when the posted write buffer fills. When the Memory Write and Invalidate transaction is disconnected before a cache line boundary is reached, typically because the posted write buffer fills, the trans-action is converted to Memory Write transaction.
4.6.3
DELAYED WRITE TRANSACTIONS
Delayed write forwarding is used for I/O write transactions and Type 1 configuration write transactions. A delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the initiating bus in wait states. A delayed write transaction is limited to a single DWORD data transfer.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION When a write transaction is first detected on the initiator bus, and PI7C7300A forwards it as a delayed transaction, PI7C7300A claims the access by asserting DEVSEL# and returns a target retry to the initiator. During the address phase, PI7C7300A samples the bus command, address, and address parity one cycle later. After IRDY# is asserted, PI7C7300A also samples the first data DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction queue. The transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. When the delayed write transaction moves to the head of the delayed transaction queue and all ordering constraints with posted data are satisfied. The PI7C7300A initiates the transaction on the target bus. PI7C7300A transfers the write data to the target. If PI7C7300A receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered. If PI7C7300A is unable to deliver write data after 224 (default) or 232 (maximum) attempts, PI7C7300A will report a system error. PI7C7300A also asserts P_SERR# if the primary SERR# enable bit is set in the command register. See Section 7.4 for information on the assertion of P_SERR#. When the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the PI7C7300A claims the access by asserting DEVSEL# and returns TRDY# to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C7300A also asserts STOP# in conjunction with TRDY# to signal a target disconnect. Note that only those bytes of write data with valid byte enable bits are compared. If any of the byte enable bits are turned off (driven HIGH), the corresponding byte of write data is not compared. If the initiator repeats the write transaction before the data has been transferred to the target, PI7C7300A returns a target retry to the initiator. PI7C7300A continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, PI7C7300A does not make a new entry into the delayed transaction queue. Section 4.9.3.1 provides detailed information about how PI7C7300A responds to target termination during delayed write transactions. PI7C7300A implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction completion queue. The initial value of this timer can be set to the retry counter register offset 78h. If the initiator does not repeat the delayed write transaction before the discard timer expires, PI7C7300A discards the delayed write completion from the delayed transaction completion queue. PI7C7300A also conditionally asserts P_SERR# (see Section 7.4).
4.6.4
WRITE TRANSACTION ADDRESS BOUNDARIES
PI7C7300A imposes internal address boundaries when accepting write data. The aligned address boundaries are used to prevent PI7C7300A from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. PI7C7300A returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in Table 4-3.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Table 4-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES
Type of Transaction Delayed Write Posted Memory Write Posted Memory Write Posted Memory Write and Invalidate Posted Memory Write and Invalidate Condition All Memory write disconnect control bit = 0(1) Memory write disconnect control bit = 1(1) Cache line size 1, 2, 4, 8, 16 Cache line size = 1, 2, 4, 8, 16 Aligned Address Boundary Disconnects after one data transfer 4KB aligned address boundary Disconnects at cache line boundary 4KB aligned address boundary
Cache line boundary if posted memory write data FIFO does not have enough space for the cache line Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the configuration space.
4.6.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C7300A continues to accept posted memory write transactions as long as space for at least one DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, PI7C7300A returns a target disconnect to the initiator. Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same time. See Chapter 6 for information about how multiple posted and delayed write transactions are ordered.
4.6.6
FAST BACK-TO-BACK WRITE TRANSACTIONS
PI7C7300A can recognize and post fast back-to-back write transactions. When PI7C7300A cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit must be set in the command register for upstream write transactions, and in the bridge control register for downstream write transactions.
4.7
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing PI7C7300A. Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 4-4 shows the read behavior, prefetchable or non-prefetchable, for each type of read operation.
4.7.1
PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where PI7C7300A performs speculative DWORD reads, transferring data from the target before it is requested from the initiator. This behavior allows a prefetchable read transaction to consist of multiple data transfers. However, byte enable bits cannot be forwarded for all data phases as is done for the single data phase of the non-prefetchable read transaction. For prefetchable read transactions, PI7C7300A forces all byte enable bits to be turned on for all data phases. Page 26 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space. The amount of data that is pre-fetched depends on the type of transaction. The amount of pre-fetching may also be affected by the amount of free buffer space available in PI7C7300A, and by any read address boundaries encountered. Pre-fetching should not be used for those read transactions that have side effects in the target device, that is, control and status registers, FIFOs, and so on. The target device's base address register or registers indicate if a memory address region is prefetchable.
4.7.2
NON-PREFETCHABLE READ TRANSACTIONS
A non-prefetchable read transaction is a read transaction where PI7C7300A requests one and only one DWORD from the target and disconnects the initiator after delivery of the first DWORD of read data. Unlike prefetchable read transactions, PI7C7300A forwards the read byte enable information for the data phase. Non-prefetchable behavior is used for I/O and configuration read transactions, as well as for memory read transactions that fall into non-prefetchable memory space. If extra read transactions could have side effects, for example, when accessing a FIFO, use non-prefetchable read transactions to those locations. Accordingly, if it is important to retain the value of the byte enable bits during the data phase, use non-prefetchable read transactions. If these locations are mapped in memory space, use the memory read command and map the target into non-prefetchable (memory-mapped I/O) memory space to use non-prefetching behavior.
4.7.3
READ PREFETCH ADDRESS BOUNDARIES
PI7C7300A imposes internal read address boundaries on read pre-fetched data. When a read transaction reaches one of these aligned address boundaries, the PI7C7300A stops pre-fetched data, unless the target signals a target disconnect before the read pre-fetched boundary is reached. When PI7C7300A finishes transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched read data is delivered. Any leftover prefetched data is discarded. Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address boundary, or until the initiator de-asserts FRAME#. Section 4.7.6 describes flowthrough mode during read operations. Table 4-5 shows the read pre-fetch address boundaries for read transactions during nonflow-through mode. Table 4-4 READ PREFETCH ADDRESS BOUNDARIES
Type of Transaction Configuration Read I/O Read Memory Read Address Space Non-Prefetchable Cache (CLS) * * * Line Size Prefetch Aligned Address Boundary One DWORD (no prefetch) One DWORD (no prefetch) One DWORD (no prefetch)
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Memory Read Memory Read Memory Read Line Memory Read Line Memory Read Multiple Prefetchable Prefetchable CLS = 0 or 16 CLS = 1, 2, 4, 8, 16 CLS = 0 or 16 CLS = 1, 2, 4, 8, 16 CLS = 0 or 16 16-DWORD aligned address boundary Cache line address boundary 16-DWORD aligned address boundary Cache line boundary 32-DWORD aligned address boundary 2X of cache line boundary
Memory Read Multiple CLS = 1, 2, 4, 8, 16 - does not matter if it is prefetchable or non-prefetchable * don't care
Table 4-5 READ TRANSACTION PREFETCHING
Read Behavior Prefetching never allowed Prefetching never allowed Downstream: Prefetching used if address is prefetchable space Memory Read Upstream: Prefetching used or programmable Memory Read Line Prefetching always used Memory Read Multiple Prefetching always used See Section 5.3 for detailed information about prefetchable and non-prefetchable address spaces. Type of Transaction I/O Read Configuration Read
4.7.4
DELAYED READ REQUESTS
PI7C7300A treats all read transactions as delayed read transactions, which means that the read request from the initiator is posted into a delayed transaction queue. Read data from the target is placed in the read data queue directed toward the initiator bus interface and is transferred to the initiator when the initiator repeats the read transaction. When PI7C7300A accepts a delayed read request, it first samples the read address, read bus command, and address parity. When IRDY# is asserted, PI7C7300A then samples the byte enable bits for the first data phase. This information is entered into the delayed transaction queue. PI7C7300A terminates the transaction by signaling a target retry to the initiator. Upon reception of the target retry, the initiator is required to continue to repeat the same read transaction until at least one data transfer is completed, or until a target response (target abort or master abort) other than a target retry is received.
4.7.5
DELAYED READ COMPLETION WITH TARGET
When delayed read request reaches the head of the delayed transaction queue, PI7C7300A arbitrates for the target bus and initiates the read transaction only if all previously queued posted write transactions have been delivered. PI7C7300A uses the exact read address and read command captured from the initiator during the initial delayed read request to initiate the read transaction. If the read transaction is a nonprefetchable read, PI7C7300A drives the captured byte enable bits during the next cycle. If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero for all data phases. If PI7C7300A receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered. If the transaction is terminated via normal master termination or target disconnect after at least one data transfer has been completed, PI7C7300A does not initiate any further attempts to read more data.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION If PI7C7300A is unable to obtain read data from the target after 224 (default) or 232 (maximum) attempts, PI7C7300A will report a system error. The number of attempts is programmable. PI7C7300A also asserts P_SERR# if the primary SERR# enable bit is set in the command register. See Section 7.4 for information on the assertion of P_SERR#. Once PI7C7300A receives DEVSEL# and TRDY# from the target, it transfers the data read to the opposite direction read data queue, pointing toward the opposite inter-face, before terminating the transaction. For example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. The PI7C7300A can accept one DWORD of read data each PCI clock cycle; that is, no master wait states are inserted. The number of DWORD transferred during a delayed read transaction depends on the conditions given in Table 4-5 (assuming no disconnect is received from the target).
4.7.6
DELAYED READ COMPLETION ON INITIATOR BUS
When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the PI7C7300A transfers the data to the initiator when the initiator repeats the transaction. For memory read transactions, PI7C7300A aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. PI7C7300A returns a target disconnect along with the transfer of the last DWORD of read data to the initiator. If PI7C7300A initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded. When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. Because data is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. In this case, the read transaction is allowed to continue until the initiator terminates the trans-action, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes first. When the buffer empties, PI7C7300A reflects the stalled condition to the initiator by disconnecting the initiator with data. The initiator may retry the transaction later if data are needed. If the initiator does not need any more data, the initiator will not continue the disconnected transaction. In this case, PI7C7300A will start the master timeout timer. The remaining read data will be discarded after the master timeout timer expires. To provide better latency, if there are any other pending data for other transactions in the RDB (Read Data Buffer), the remaining read data will be discarded even though the master timeout timer has not expired. PI7C7300A implements a master timeout timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. The initial value of this timer is program-mable through configuration register. If the initiator does not repeat the read transaction and before the master timeout timer expires (215 default), PI7C7300A discards the read transaction and read data from its queues. PI7C7300A also conditionally asserts P_SERR# (see Section 7.4).
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C7300A has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted as it is already contained in the delayed transaction queue. See Section 6 for a discussion of how delayed read transactions are ordered when crossing PI7C7300A.
4.7.7
FAST BACK-TO-BACK READ TRANSACTION
PI7C7300A can recognize fast back-to-back read transactions.
4.8
CONFIGURATION TRANSACTIONS
Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All registers are accessible in configuration space only. In addition to accepting configuration transactions for initialization of its own configuration space, the PI7C7300A also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation. To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1. Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b. Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b. The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted.
4.8.1
TYPE 0 ACCESS TO PI7C7300A
The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration space cannot be accessed from the secondary bus. The PI7C7300A responds to a Type 0 configuration transaction by asserting P_DEVSEL# when the following conditions are met during the address phase: Page 30 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! ! ! The bus command is a configuration read or configuration write transaction. Lowest two address bits P_AD[1:0] must be 00b. Signal P_IDSEL must be asserted.
Function code is either 0 for configuration space of S1, or 1 for configuration space of S2 as PI7C7300A is a multi-function device. PI7C7300A limits all configuration access to a single DWORD data transfer and returns target-disconnect with the first data transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects, all bytes in the requested DWORD are returned, regardless of the value of the byte enable bits. Type 0 configuration write and read transactions do not use data buffers; that is, these transactions are completed immediately, regardless of the state of the data buffers. The PI7C7300A ignores all Type 0 transactions initiated on the secondary interface.
4.8.2
TYPE 1 TO TYPE 0 CONVERSION
Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. PI7C7300A performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C7300A must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction; that is, PI7C7300A generates a Type 0 transaction only on the secondary bus, and never on the primary bus. PI7C7300A responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase: ! ! ! The lowest two address bits on P_AD[1:0] are 01b. The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space. The bus command on P_CBE[3:0] is a configuration read or configuration write transaction.
When PI7C7300A translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it performs the following translations to the address: ! Sets the lowest two address bits on S1_AD[1:0] or S2_AD[1:0] to 00b.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! Decodes the device number and drives the bit pattern specified in Table 4-6 on S1_AD[31:16] or S2_AD[31:16] for the purpose of asserting the device's IDSEL signal. Sets S1_AD[15:11] or S2_AD[15:11] to 0. Leaves unchanged the function number and register number fields.
! !
PI7C7300A asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the Type 1 address bits P_AD[15:11]. Table 4-6 presents the mapping that PI7C7300A uses. Table 4-6 DEVICE NUMBER TO IDSEL S1_AD OR S2_AD PIN MAPPING
Device Number 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h - 1Eh 1Fh P_AD[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 - 11110 11111 Secondary IDSEL S1_AD[31:16] S2_AD[31:16] 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 Generate special cycle (P_AD[7:2] = 00h) 0000 0000 0000 0000 (P_AD[7:2] = 00h) or S1_AD S2_AD 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 or
PI7C7300A can assert up to 16 unique address lines to be used as IDSEL signals for up to 16 devices on the secondary bus, for device numbers ranging from 0 through 15. Because of electrical loading constraints of the PCI bus, more than 16 IDSEL signals should not be necessary. However, if device numbers greater than 15 are desired, some external method of generating IDSEL lines must be used, and no upper address bits are then asserted. The configuration transaction is still translated and passed from the primary bus to the secondary bus. If no IDSEL pin is asserted to a secondary device, the transaction ends in a master abort. PI7C7300A forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions. Type 1 to Type 0 configuration read or write transactions are limited to a single 32-bit data transfer.
4.8.3
TYPE 1 TO TYPE 1 FORWARDING
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-to-PCI bridges are used.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION When PI7C7300A detects a Type 1 configuration transaction intended for a PCI bus downstream from the secondary bus, PI7C7300A forwards the transaction unchanged to the secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met during the address phase: ! ! The lowest two address bits are equal to 01b. The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The bus command is a configuration read or write transaction.
!
PI7C7300A also supports Type 1 to Type 1 forwarding of configuration write transactions upstream to support upstream special cycle generation. A Type 1 configuration command is forwarded upstream when the following conditions are met: ! ! The lowest two address bits are equal to 01b. The bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The device number in address bits AD[15:11] is equal to 11111b. The function number in address bits AD[10:8] is equal to 111b. The bus command is a configuration write transaction.
! ! !
The PI7C7300A forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1 configuration write transactions are limited to a single data transfer.
4.8.4
SPECIAL CYCLES
The Type 1 configuration mechanism is used to generate special cycle transactions in hierarchical PCI systems. Special cycle transactions are ignored by acting as a target and are not forwarded across the bridge. Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the down-stream direction. PI7C7300A initiates a special cycle on the target bus when a Type 1 configuration write transaction is being detected on the initiating bus and the following conditions are met during the address phase: ! ! ! The lowest two address bits on AD[1:0] are equal to 01b. The device number in address bits AD[15:11] is equal to 11111b. The function number in address bits AD[10:8] is equal to 111b. Page 33 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! ! The register number in address bits AD[7:2] is equal to 000000b. The bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding. The bus command on CBE# is a configuration write command.
!
When PI7C7300A initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. The address and data are for-warded unchanged. Devices that use special cycles ignore the address and decode only the bus command. The data phase contains the special cycle message. The transaction is forwarded as a delayed transaction, but in this case the target response is not forwarded back (because special cycles result in a master abort). Once the transaction is completed on the target bus, through detection of the master abort condition, PI7C7300A responds with TRDY# to the next attempt of the con-figuration transaction from the initiator. If more than one data transfer is requested, PI7C7300A responds with a target disconnect operation during the first data phase.
4.9
TRANSACTION TERMINATION
This section describes how PI7C7300A returns transaction termination conditions back to the initiator. The initiator can terminate transactions with one of the following types of termination: ! Normal termination Normal termination occurs when the initiator de-asserts FRAME# at the beginning of the last data phase, and de-asserts IRDY# at the end of the last data phase in conjunction with either TRDY# or STOP# assertion from the target. ! Master abort A master abort occurs when no target response is detected. When the initiator does not detect a DEVSEL# from the target within five clock cycles after asserting FRAME#, the initiator terminates the transaction with a master abort. If FRAME# is still asserted, the initiator de-asserts FRAME# on the next cycle, and then de-asserts IRDY# on the following cycle. IRDY# must be asserted in the same cycle in which FRAME# deasserts. If FRAME# is already de-asserted, IRDY# can be de-asserted on the next clock cycle following detection of the master abort condition. The target can terminate transactions with one of the following types of termination: ! Normal termination TRDY# and DEVSEL# asserted in conjunction with FRAME# de-asserted and IRDY# asserted. ! Target retry STOP# and DEVSEL# asserted with TRDY# de-asserted during the first data phase. No data transfers occur during the transaction. This transaction must be repeated. ! Target disconnect with data transfer Page 34 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the transaction. ! Target disconnect without data transfer STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been made. Indicates that no more data transfers will be made during this transaction. ! Target abort STOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will never be able to complete this transaction. DEVSEL# must be asserted for at least one cycle during the transaction before the target abort is signaled.
4.9.1
MASTER TERMINATION INITIATED BY PI7C7300A
PI7C7300A, as an initiator, uses normal termination if DEVSEL# is returned by target within five clock cycles of PI7C7300A's assertion of FRAME# on the target bus. As an initiator, PI7C7300A terminates a transaction when the following conditions are met: ! ! ! ! ! During a delayed write transaction, a single DWORD is delivered. During a non-prefetchable read transaction, a single DWORD is transferred from the target. During a prefetchable read transaction, a pre-fetch boundary is reached. For a posted write transaction, all write data for the transaction is transferred from data buffers to the target. For burst transfer, with the exception of "Memory Write and Invalidate" transactions, the master latency timer expires and the PI7C7300A's bus grant is deasserted. The target terminates the transaction with a retry, disconnect, or target abort.
!
If PI7C7300A is delivering posted write data when it terminates the transaction because the master latency timer expires, it initiates another transaction to deliver the remaining write data. The address of the transaction is updated to reflect the address of the current DWORD to be delivered. If PI7C7300A is pre-fetching read data when it terminates the transaction because the master latency timer expires, it does not repeat the transaction to obtain more data.
4.9.2
MASTER ABORT RECEIVED BY PI7C7300A
If the initiator initiates a transaction on the target bus and does not detect DEVSEL# returned by the target within five clock cycles of the assertion of FRAME#, PI7C7300A terminates the transaction with a master abort. This sets the received-master-abort bit in the status register corresponding to the target bus.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION For delayed read and write transactions, PI7C7300A is able to reflect the master abort condition back to the initiator. When PI7C7300A detects a master abort in response to a delayed transaction, and when the initiator repeats the transaction, PI7C7300A does not respond to the transaction with DEVSEL# which induces the master abort condition back to the initiator. The transaction is then removed from the delayed transaction queue. When a master abort is received in response to a posted write transaction, PI7C7300A discards the posted write data and makes no more attempts to deliver the data. PI7C7300A sets the received-master-abort bit in the status register when the master abort is received on the primary bus, or it sets the received master abort bit in the secondary status register when the master abort is received on the secondary interface. When master abort is detected in posted write transaction with both master-abort-mode bit (bit 5 of bridge control register) and the SERR# enable bit (bit 8 of command register for secondary bus S1 or S2) are set, PI7C7300A asserts P_SERR# if the master-abort-onposted-write is not set. The master-abort-on-posted-write bit is bit 4 of the P_SERR# event disable register (offset 64h). Note: When PI7C7300A performs a Type 1 to special cycle conversion, a master abort is the expected termination for the special cycle on the target bus. In this case, the master abort received bit is not set, and the Type 1 configuration transaction is disconnected after the first data phase.
4.9.3
TARGET TERMINATION RECEIVED BY PI7C7300A
When PI7C7300A initiates a transaction on the target bus and the target responds with DEVSEL#, the target can end the transaction with one of the following types of termination: ! ! ! ! Normal termination (upon de-assertion of FRAME#) Target retry Target disconnect Target abort
PI7C7300A handles these terminations in different ways, depending on the type of transaction being performed. 4.9.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE When PI7C7300A initiates a delayed write transaction, the type of target termination received from the target can be passed back to the initiator. Table 4-7 shows the response to each type of target termination that occurs during a delayed write transaction. PI7C7300A repeats a delayed write transaction until one of the following conditions is met: ! ! ! PI7C7300A completes at least one data transfer. PI7C7300A receives a master abort. PI7C7300A receives a target abort. Page 36 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C7300A makes 224 (default) or 232 (maximum) write attempts resulting in a response of target retry. Table 4-7 DELAYED WRITE TARGET TERMINATION RESPONSE
Target Termination Normal Target Retry Target Disconnect Target Abort Response Returning disconnect to initiator with first data transfer only if multiple data phases requested. Returning target retry to initiator. Continue write attempts to target Returning disconnect to initiator with first data transfer only if multiple data phases requested. Returning target abort to initiator. Set received target abort bit in target interface status register. Set signaled target abort bit in initiator interface status register.
After the PI7C7300A makes 224 (default) attempts of the same delayed write trans-action on the target bus, PI7C7300A asserts P_SERR# if the SERR# enable bit (bit 8 of command register for secondary bus S1 or S2) is set and the delayed-write-non- delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register (offset 64h). PI7C7300A will report system error. See Section 7.4 for a description of system error conditions. 4.9.3.2 POSTED WRITE TARGET TERMINATION RESPONSE When PI7C7300A initiates a posted write transaction, the target termination cannot be passed back to the initiator. Table 4-8 shows the response to each type of target termination that occurs during a posted write transaction. Table 4-8 RESPONSE TO POSTED WRITE TARGET TERMINATION
Target Termination Normal Target Retry Target Disconnect Target Abort Repsonse No additional action. Repeating write transaction to target. Initiate write transaction for delivering remaining posted write data. Set received-target-abort bit in the target interface status register. Assert P_SERR# if enabled, and set the signaled-system-error bit in primary status register.
Note that when a target retry or target disconnect is returned and posted write data associated with that transaction remains in the write buffers, PI7C7300A initiates another write transaction to attempt to deliver the rest of the write data. If there is a target retry, the exact same address will be driven as for the initial write trans-action attempt. If a target disconnect is received, the address that is driven on a subsequent write transaction attempt will be updated to reflect the address of the current DWORD. If the initial write transaction is Memory-Write-and-Invalidate transaction, and a partial delivery of write data to the target is performed before a target disconnect is received, PI7C7300A will use the memory write command to deliver the rest of the write data. It is because an incomplete cache line will be transferred in the subsequent write transaction attempt. After the PI7C7300A makes 224 (default) write transaction attempts and fails to deliver all posted write data associated with that transaction, PI7C7300A asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for secondary bus S1 or S2) and posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2 of P_SERR# event disable register (offset 64h). PI7C7300A will report system error. See Section 7.4 for a discussion of system error conditions.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 4.9.3.3 DELAYED READ TARGET TERMINATION RESPONSE When PI7C7300A initiates a delayed read transaction, the abnormal target responses can be passed back to the initiator. Other target responses depend on how much data the initiator requests. Table 4-9 shows the response to each type of target termination that occurs during a delayed read transaction. PI7C7300A repeats a delayed read transaction until one of the following conditions is met: ! ! ! ! PI7C7300A completes at least one data transfer. PI7C7300A receives a master abort. PI7C7300A receives a target abort. PI7C7300A makes 224 (default) read attempts resulting in a response of target retry.
Table 4-9 RESPONSE TO DELAYED READ TARGET TERMINATION
Target Termination Normal Target Retry Target Disconnect Target Abort Response If prefetchable, target disconnect only if initiator requests more data than read from target. If non-prefetchable, target disconnect on first data phase. Re-initiate read transaction to target If initiator requests more data than read from target, return target disconnect to initiator. Return target abort to initiator. Set received target abort bit in the target interface status register. Set signaled target abort bit in the initiator interface status register.
After PI7C7300A makes 224(default) attempts of the same delayed read transaction on the target bus, PI7C7300A asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for secondary bus S1 or S2) and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register (offset 64h). PI7C7300A will report system error. See Section 7.4 for a description of system error conditions.
4.9.4
TARGET TERMINATION INITIATED BY PI7C7300A
PI7C7300A can return a target retry, target disconnect, or target abort to an initiator for reasons other than detection of that condition at the target interface.
4.9.4.1
TARGET RETRY PI7C7300A returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. PI7C7300A returns a target retry to an initiator when any of the following conditions is met: For delayed write transactions: ! ! The transaction is being entered into the delayed transaction queue. Transaction has already been entered into delayed transaction queue, but target response has not yet been received. Page 38 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! ! ! ! ! ! Target response has been received but has not progressed to the head of the return queue. The delayed transaction queue is full, and the transaction cannot be queued. A transaction with the same address and command has been queued. A locked sequence is being propagated across PI7C7300A, and the write transaction is not a locked transaction. The target bus is locked and the write transaction is a locked transaction. Use more than 16 clocks to accept this transaction.
For delayed read transactions: ! ! ! ! ! ! ! ! ! The transaction is being entered into the delayed transaction queue. The read request has already been queued, but read data is not yet available. Data has been read from target, but it is not yet at head of the read data queue or a posted write transaction precedes it. The delayed transaction queue is full, and the transaction cannot be queued. A delayed read request with the same address and bus command has already been queued. A locked sequence is being propagated across PI7C7300A, and the read transaction is not a locked transaction. PI7C7300A is currently discarding previously pre-fetched read data. The target bus is locked and the write transaction is a locked transaction. Use more than 16 clocks to accept this transaction.
For posted write transactions: ! ! The posted write data buffer does not have enough space for address and at least one DWORD of write data. A locked sequence is being propagated across PI7C7300A, and the write transaction is not a locked transaction.
When a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the transaction with the same address and bus command as well as the data if it is a write transaction, within the time frame specified by the master timeout value. Otherwise, the transaction is discarded from the buffers. 4.9.4.2 TARGET DISCONNECT
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C7300A returns a target disconnect to an initiator when one of the following conditions is met: ! ! ! PI7C7300A hits an internal address boundary. PI7C7300A cannot accept any more write data. PI7C7300A has no more read data to deliver.
See Section 4.6.4 for a description of write address boundaries, and Section 4.7.3 for a description of read address boundaries. 4.9.4.3 TARGET ABORT PI7C7300A returns a target abort to an initiator when one of the following conditions is met: ! PI7C7300A is returning a target abort from the intended target.
When PI7C7300A returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface.
4.10
CONCURRENT MODE OPERATION
The Bridge can be configured to run in concurrent operation. Concurrent operation is defined as cycles going from one device on one secondary bus to another device on the same or other secondary bus. This off-loads traffic from the primary bus, allowing other traffic to run on the primary bus concurrently. The Bridge is already configured to handle concurrent operation. However, the devices themselves need to be configured to do so. Meaning, device drivers for the specific device used will have to be configured to perform the operation. Please see section 5.1 for more information on addressing.
5
ADDRESS DECODING
PI7C7300A uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the configuration space. This chapter describes these address ranges, as well as ISA-mode and VGA-addressing support.
5.1
ADDRESS RANGES
PI7C7300A uses the following address ranges that determine which I/O and memory transactions are forwarded from the primary PCI bus to the secondary PCI bus, and from the secondary bus to the primary bus: Page 40 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! ! ! Two 32-bit I/O address ranges Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges Two 32-bit prefetchable memory address ranges
Transactions falling within these ranges are forwarded downstream from the primary PCI bus to the two secondary PCI buses. Transactions falling outside these ranges are forwarded upstream from the two secondary PCI buses to the primary PCI bus. No address translation is required in PI7C7300A. The addresses that are not marked for downstream are always forwarded upstream. However, if an address of a transaction initiated from S1 bus is located in the marked address range for down-stream in S2 bus and not in the marked address range for downstream in S1 bus, the transaction will be forwarded to S2 bus instead of primary bus. By the same token, if an address of a transaction initiated from S2 bus is located in the marked address range for downstream in S1 bus and not in the marked address range for downstream in S2 bus, the transaction will be forwarded to S1 bus instead of primary bus.
5.2
I/O ADDRESS DECODING
PI7C7300A uses the following mechanisms that are defined in the configuration space to specify the I/O address space for downstream and upstream forwarding: ! ! ! ! I/O base and limit address registers The ISA enable bit The VGA mode bit The VGA snoop bit
This section provides information on the I/O address registers and ISA mode. Section 5.4 provides information on the VGA modes. To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the command register in configuration space. All I/O transactions initiated on the primary bus will be ignored if the I/O enable bit is not set. To enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the masterenable bit is not set, PI7C7300A ignores all I/O and memory transactions initiated on the secondary bus. The master-enable bit also allows upstream forwarding of memory transactions if it is set. CAUTION If any configuration state affecting I/O transaction forwarding is changed by a configuration write operation on the primary bus at the same time that I/O transactions are ongoing on the secondary bus, PI7C7300A response to the secondary bus I/O transactions is not predictable. Configure the I/O base and limit address registers, ISA enable bit, VGA mode bit, and VGA snoop bit before setting I/O enable Page 41 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.
5.2.1
I/O BASE AND LIMIT ADDRESS REGISTER
PI7C7300A implements one set of I/O base and limit address registers in configuration space that define an I/O address range per port downstream forwarding. PI7C7300A supports 32-bit I/O addressing, which allows I/O addresses downstream of PI7C7300A to be mapped anywhere in a 4GB I/O address space. I/O transactions with addresses that fall inside the range defined by the I/O base and limit registers are forwarded downstream from the primary PCI bus to the secondary PCI bus. I/O transactions with addresses that fall outside this range are forwarded upstream from the secondary PCI bus to the primary PCI bus. The I/O range can be turned off by setting the I/O base address to a value greater than that of the I/O limit address. When the I/O range is turned off, all I/O trans-actions are forwarded upstream, and no I/O transactions are forwarded downstream. The I/O range has a minimum granularity of 4KB and is aligned on a 4KB boundary. The maximum I/O range is 4GB in size. The I/O base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at address 30h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O base address. The bottom 4 bits read only as 1h to indicate that PI7C7300A supports 32-bit I/O addressing. Bits [11:0] of the base address are assumed to be 0, which naturally aligns the base address to a 4KB boundary. The 16 bits contained in the I/O base upper 16 bits register at configuration offset 30h define AD[31:16] of the I/O base address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O base address is initialized to 0000 0000h. The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit field at offset 32h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O limit address. The bottom 4 bits read only as 1h to indicate that 32-bit I/O addressing is supported. Bits [11:0] of the limit address are assumed to be FFFh, which naturally aligns the limit address to the top of a 4KB I/O address block. The 16 bits contained in the I/O limit upper 16 bits register at configuration offset 32h define AD[31:16] of the I/O limit address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O limit address is reset to 0000 0FFFh. Note: The initial states of the I/O base and I/O limit address registers define an I/O range of 0000 0000h to 0000 0FFFh, which is the bottom 4KB of I/O space. Write these registers with their appropriate values before setting either the I/O enable bit or the master enable bit in the command register in configuration space.
5.2.2
ISA MODE
PI7C7300A supports ISA mode by providing an ISA enable bit in the bridge control register in configuration space. ISA mode modifies the response of PI7C7300A inside the I/O address range in order to support mapping of I/O space in the presence of an ISA bus in the system. This bit only affects the response of PI7C7300A when the transaction falls inside the address range defined by the I/O base and limit address registers, and only Page 42 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION when this address also falls inside the first 64KB of I/O space (address bits [31:16] are 0000h). When the ISA enable bit is set, PI7C7300A does not forward downstream any I/O transactions addressing the top 768 bytes of each aligned 1KB block. Only those transactions addressing the bottom 256 bytes of an aligned 1KB block inside the base and limit I/O address range are forwarded downstream. Transactions above the 64KB I/O address boundary are forwarded as defined by the address range defined by the I/O base and limit registers. Accordingly, if the ISA enable bit is set, PI7C7300A forwards upstream those I/O transactions addressing the top 768 bytes of each aligned 1KB block within the first 64KB of I/O space. The master enable bit in the command configuration register must also be set to enable upstream forwarding. All other I/O transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O address range. When the ISA enable bit is set, devices downstream of PI7C7300A can have I/O space mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary.
5.3
MEMORY ADDRESS DECODING
PI7C7300A has three mechanisms for defining memory address ranges for forwarding of memory transactions: ! ! ! Memory-mapped I/O base and limit address registers Prefetchable memory base and limit address registers VGA mode
This section describes the first two mechanisms. Section 5.4.1 describes VGA mode. To enable downstream forwarding of memory transactions, the memory enable bit must be set in the command register in configuration space. To enable upstream forwarding of memory transactions, the master-enable bit must be set in the command register. The master-enable bit also allows upstream forwarding of I/O transactions if it is set. CAUTION If any configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus at the same time that memory transactions are ongoing on the secondary bus, response to the secondary bus memory transactions is not predictable. Configure the memory-mapped I/O base and limit address registers, prefetchable memory base and limit address registers, and VGA mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.
5.3.1
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS
Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses that cannot automatically be pre-fetched but that can be conditionally prefetched based on command type should be mapped into this space. Read trans-actions to nonprefetchable space may exhibit side effects; this space may have non-memory-like behavior. PI7C7300A prefetches in this space only if the memory read line or memory Page 43 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION read multiple commands are used; transactions using the memory read command are limited to a single data transfer. The memory-mapped I/O base address and memory-mapped I/O limit address registers define an address range that PI7C7300A uses to determine when to forward memory commands. PI7C7300A forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the memory-mapped I/O address range. PI7C7300A ignores memory transactions initiated on the secondary interface that fall into this address range. Any transactions that fall outside this address range are ignored on the primary interface and are forwarded upstream from the secondary interface (provided that they do not fall into the prefetchable memory range or are not forwarded downstream by the VGA mechanism). The memory-mapped I/O range supports 32-bit addressing only. The PCI-to-PCI Bridge Architecture Specification does not provide for 64-bit addressing in the memory-mapped I/O space. The memory-mapped I/O address range has a granularity and alignment of 1MB. The maximum memory-mapped I/O address range is 4GB. The memory-mapped I/O address range is defined by a 16-bit memory-mapped I/O base address register at configuration offset 20h and by a 16-bit memory-mapped I/O limit address register at offset 22h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The low 4 bits are hardwired to 0. The lowest 20 bits of the memory-mapped I/O base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The lowest 20 bits of the memory-mapped I/O limit address are assumed to be FFFFFh, which results in an alignment to the top of a 1MB block. Note: The initial state of the memory-mapped I/O base address register is 0000 0000h. The initial state of the memory-mapped I/O limit address register is 000F FFFFh. Note that the initial states of these registers define a memory-mapped I/O range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. To turn off the memory-mapped I/O address range, write the memory-mapped I/O base address register with a value greater than that of the memory-mapped I/O limit address register.
5.3.2
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS
Locations accessed in the prefetchable memory address range must have true memorylike behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable memory location must have no side effects. PI7C7300A pre-fetches for all types of memory read commands in this address space. The prefetchable memory base address and prefetchable memory limit address registers define an address range that PI7C7300A uses to determine when to for- ward memory commands. PI7C7300A forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the prefetchable memory address range. PI7C7300A ignores memory transactions initiated on the secondary Page 44 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION interface that fall into this address range. PI7C7300A does not respond to any transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that they do not fall into the memory-mapped I/O range or are not forwarded by the VGA mechanism). The prefetchable memory range supports 64-bit addressing and provides additional registers to define the upper 32 bits of the memory address range, the prefetchable memory base address upper 32 bits register, and the prefetchable memory limit address upper 32 bits register. For address comparison, a single address cycle (32-bit address) prefetchable memory transaction is treated like a 64-bit address transaction where the upper 32 bits of the address are equal to 0. This upper 32-bit value of 0 is compared to the prefetchable memory base address upper 32 bits register and the prefetchable memory limit address upper 32 bits register. The prefetchable memory base address upper 32 bits register must be 0 to pass any single address cycle transactions downstream. Prefetchable memory address range has a granularity and alignment of 1MB. Maximum memory address range is 4GB when 32-bit addressing is being used. Prefetchable memory address range is defined by a 16-bit prefetchable memory base address register at configuration offset 24h and by a 16-bit prefetchable memory limit address register at offset 26h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The lowest 4 bits are hardwired to 1h. The lowest 20 bits of the prefetchable memory base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The lowest 20 bits of the prefetchable memory limit address are assumed to be FFFFFh, which results in an alignment to the top of a 1MB block. Note: The initial state of the prefetchable memory base address register is 0000 0000h. The initial state of the prefetchable memory limit address register is 000F FFFFh. Note that the initial states of these registers define a prefetchable memory range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. To turn off the prefetchable memory address range, write the prefetchable memory base address register with a value greater than that of the prefetchable memory limit address register. The entire base value must be greater than the entire limit value, meaning that the upper 32 bits must be considered. Therefore, to disable the address range, the upper 32 bits registers can both be set to the same value, while the lower base register is set greater than the lower limit register. Otherwise, the upper 32-bit base must be greater than the upper 32-bit limit.
5.4
VGA SUPPORT
PI7C7300A provides two modes for VGA support: ! ! VGA mode, supporting VGA-compatible addressing VGA snoop mode, supporting VGA palette forwarding
5.4.1
VGA MODE
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION When a VGA-compatible device exists downstream from PI7C7300A, set the VGA mode bit in the bridge control register in configuration space to enable VGA mode. When PI7C7300A is operating in VGA mode, it forwards downstream those transactions addressing the VGA frame buffer memory and VGA I/O registers, regardless of the values of the base and limit address registers. PI7C7300A ignores transactions initiated on the secondary interface addressing these locations. The VGA frame buffer consists of the following memory address range: 000A 0000h-000B FFFFh Read transactions to frame buffer memory are treated as non-prefetchable. PI7C7300A requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus. The VGA I/O addresses are in the range of 3B0h-3BBh and 3C0h-3DFh I/O. These I/O addresses are aliases every 1KB throughout the first 64KB of I/O space. This means that address bits <15:10> are not decoded and can be any value, while address bits [31:16] must be all 0s. VGA BIOS addresses starting at C0000h are not decoded in VGA mode.
5.4.2
VGA SNOOP MODE
PI7C7300A provides VGA snoop mode, allowing for VGA palette write transactions to be forwarded downstream. This mode is used when a graphics device downstream from PI7C7300A needs to snoop or respond to VGA palette write transactions. To enable the mode, set the VGA snoop bit in the command register in configuration space. Note that PI7C7300A claims VGA palette write transactions by asserting DEVSEL# in VGA snoop mode. When VGA snoop bit is set, PI7C7300A forwards downstream transactions within the 3C6h, 3C8h and 3C9h I/O addresses space. Note that these addresses are also forwarded as part of the VGA compatibility mode previously described. Again, address bits <15:10> are not decoded, while address bits <31:16> must be equal to 0, which means that these addresses are aliases every 1KB throughout the first 64KB of I/O space. Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C7300A behaves in the same way as if only the VGA mode bit were set.
6
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C7300A complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.2, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction forwarding across PI7C7300A.
6.1
TRANSACTIONS GOVERNED BY ORDERING RULES
Ordering relationships are established for the following classes of transactions crossing PI7C7300A:
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Posted write transactions, comprised of memory write and memory write and invalidate transactions. Posted write transactions complete at the source before they complete at the destination; that is, data is written into intermediate data buffers before it reaches the target. Delayed write request transactions, comprised of I/O write and configuration write transactions. Delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. A delayed write transaction must complete on the target bus before it completes on the initiator bus. Delayed write completion transactions, comprised of I/O write and configuration write transactions. Delayed write completion transactions complete on the target bus, and the target response is queued in the buffers. A delayed write completion transaction proceeds in the direction opposite that of the original delayed write request; that is, a delayed write completion transaction proceeds from the target bus to the initiator bus. Delayed read request transactions, comprised of all memory read, I/O read, and configuration read transactions. Delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. Delayed read completion transactions, comprised of all memory read, I/O read, & configuration read transactions. Delayed read completion transactions complete on the target bus, and the read data is queued in the read data buffers. A delayed read completion transaction proceeds in the direction opposite that of the original delayed read request; that is, a delayed read completion transaction proceeds from the target bus to the initiator bus. PI7C7300A does not combine or merge write transactions: ! ! PI7C7300A does not combine separate write transactions into a single write transaction--this optimization is best implemented in the originating master. PI7C7300A does not merge bytes on separate masked write transactions to the same DWORD address--this optimization is also best implemented in the originating master. PI7C7300A does not collapse sequential write transactions to the same address into a single write transaction--the PCI Local Bus Specification does not permit this combining of transactions.
!
6.2
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when those transactions cross PI7C7300A. The following general ordering guidelines govern transactions crossing PI7C7300A:
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! The ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry. Requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. If the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. If more than one delayed transaction is initiated, the initiator should repeat all delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction cannot be contingent on completion of another delayed transaction. Otherwise, a deadlock can occur. Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. PI7C7300A can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time. The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for PI7C7300A and must also be true for other bus agents. Otherwise, a deadlock can occur. PI7C7300A accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C7300A.
!
!
!
!
6.3
ORDERING RULES
Table 6-1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow. Table 6-1 SUMMARY OF TRANSACTION ORDERING
Pass Posted Write Delayed Read Request Delayed Write Request Delayed Read Completion Delayed Write Completion Posted Write No1 No2 No4 No3 Yes Delayed Read Request Yes5 No No Yes Yes Delayed Write Request Yes5 No No Yes Yes Delayed Read Completion Yes5 Yes Yes No No Delayed Write Completion Yes5 Yes Yes No No
Note: The superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section. Many entries are not governed by these ordering rules; therefore, the implementation can choose whether or not the transactions pass each other. The entries without superscripts reflect the PI7C7300A's implementation choices. The following ordering rules describe the transaction relationships. Each ordering rule is followed by an explanation, and the ordering rules are referred to by number in Table 6-1. These ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing PI7C7300A in the
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION same direction. Note that delayed completion transactions cross PI7C7300A in the direction opposite that of the corresponding delayed requests. 1. Posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. The subsequent posted write transaction can be setting a flag that covers the data in the first posted write transaction; if the second transaction were to complete before the first transaction, a device checking the flag could subsequently consume stale data. A delayed read request traveling in the same direction as a previously queued posted write transaction must push the posted write data ahead of it. The posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. The read transaction can be to the same location as the write data, so if the read transaction were to pass the write transaction, it would return stale data. A delayed read completion must ``pull'' ahead of previously queued posted write data traveling in the same direction. In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C7300A as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator. The read transaction can be a reading to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete. Delayed write requests cannot pass previously queued posted write data. For posted memory write transactions, the delayed write transaction can set a flag that covers the data in the posted write transaction. If the delayed write request were to complete before the earlier posted write transaction, a device checking the flag could subsequently consume stale data. Posted write transactions must be given opportunities to pass delayed read and write requests and completions. Otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do not support delayed transactions are being used in the same system. A fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue.
2.
3.
4.
5.
6.4
DATA SYNCHRONIZATION
Data synchronization refers to the relationship between interrupt signaling and data delivery. The PCI Local Bus Specification, Revision 2.2, provides the following alternative methods for synchronizing data and interrupts: ! ! The device signaling the interrupt performs a read of the data just written (software). The device driver performs a read operation to any register in the interrupting device before accessing data written by the device (software).
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! System hardware guarantees that write buffers are flushed before interrupts are forwarded.
PI7C7300A does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location along the same path), or from the device driver to one of the device registers.
7
ERROR HANDLING
PI7C7300A checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, PI7C7300A always tries to forward the existing parity condition on one bus to the other bus, along with address and data. PI7C100 always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions. To support error reporting on the PCI bus, PI7C7300A implements the following: ! ! ! PERR# and SERR# signals on both the primary and secondary interfaces Primary status and secondary status registers The device-specific P_SERR# event disable register
This chapter provides detailed information about how PI7C7300A handles errors. It also describes error status reporting and error operation disabling.
7.1
ADDRESS PARITY ERRORS
PI7C7300A checks address parity for all transactions on both buses, for all address and all bus commands. When PI7C7300A detects an address parity error on the primary interface, the following events occur: ! If the parity error response bit is set in the command register, PI7C7300A does not claim the transaction with P_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C7300A proceeds normally and accepts the transaction if it is directed to or across PI7C7300A. PI7C7300A sets the detected parity error bit in the status register. PI7C7300A asserts P_SERR# and sets signaled system error bit in the status register, if both the following conditions are met: The SERR# enable bit is set in the command register. The parity error response bit is set in the command register.
! !
When PI7C7300A detects an address parity error on the secondary interface, the following events occur:
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! If the parity error response bit is set in the bridge control register, PI7C7300A does not claim the transaction with S1_DEVSEL# or S2_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C7300A proceeds normally and accepts transaction if it is directed to or across PI7C7300A. PI7C7300A sets the detected parity error bit in the secondary status register. PI7C7300A asserts P_SERR# and sets signaled system error bit in status register, if both of the following conditions are met: The SERR# enable bit is set in the command register. The parity error response bit is set in the bridge control register.
! !
7.2
DATA PARITY ERRORS
When forwarding transactions, PI7C7300A attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition. The following sections describe, for each type of transaction, the sequence of events that occurs when a parity error is detected and the way in which the parity condition is forwarded across PI7C7300A.
7.2.1
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE
When PI7C7300A detects a data parity error during a Type 0 configuration write transaction to PI7C7300A configuration space, the following events occur: ! If the parity error response bit is set in the command register, PI7C7300A asserts P_TRDY# and writes the data to the configuration register. PI7C7300A also asserts P_PERR#. If the parity error response bit is not set, PI7C7300A does not assert P_PERR#. PI7C7300A sets the detected parity error bit in the status register, regardless of the state of the parity error response bit.
!
7.2.2
READ TRANSACTIONS
When PI7C7300A detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts PERR#. For downstream transactions, when PI7C7300A detects a read data parity error on the secondary bus, the following events occur: ! ! PI7C7300A asserts S_PERR# two cycles following the data transfer, if the secondary interface parity error response bit is set in the bridge control register. PI7C7300A sets the detected parity error bit in the secondary status register. Page 51 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! ! PI7C7300A sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. PI7C7300A forwards the bad parity with the data back to the initiator on the primary bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is discarded and the data with bad parity is not returned to the initiator. PI7C7300A completes the transaction normally.
!
For upstream transactions, when PI7C7300A detects a read data parity error on the primary bus, the following events occur: ! ! ! ! PI7C7300A asserts P_PERR# two cycles following the data transfer, if the primary interface parity error response bit is set in the command register. PI7C7300A sets the detected parity error bit in the primary status register. PI7C7300A sets the data parity detected bit in the primary status register, if the primary interface parity-error-response bit is set in the command register. PI7C7300A forwards the bad parity with the data back to the initiator on the secondary bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus, the data is discarded and the data with bad parity is not returned to the initiator. PI7C7300A completes the transaction normally.
!
PI7C7300A returns to the initiator the data and parity that was received from the target. When the initiator detects a parity error on this read data and is enabled to report it, the initiator asserts PERR# two cycles after the data transfer occurs. It is assumed that the initiator takes responsibility for handling a parity error condition; therefore, when PI7C7300A detects PERR# asserted while returning read data to the initiator, PI7C7300A does not take any further action and completes the transaction normally.
7.2.3
DELAYED WRITE TRANSACTIONS
When PI7C7300A detects a data parity error during a delayed write transaction, the initiator drives data and data parity, and the target checks parity and conditionally asserts PERR#. For delayed write transactions, a parity error can occur at the following times: ! ! ! During the original delayed write request transaction When the initiator repeats the delayed write request transaction When PI7C7300A completes the delayed write transaction to the target
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION to the initiator. When PI7C7300A detects a parity error on the write data for the initial delayed write request transaction, the following events occur: ! If the parity-error-response bit corresponding to the initiator bus is set, PI7C7300A asserts TRDY# to the initiator and the transaction is not queued. If multiple data phases are requested, STOP# is also asserted to cause a target disconnect. Two cycles after the data transfer, PI7C7300A also asserts PERR#. If the parity-error-response bit is not set, PI7C7300A returns a target retry. It queues the transaction as usual. PI7C7300A does not assert PERR#. In this case, the initiator repeats the transaction. ! PI7C7300A sets the detected-parity-error bit in the status register corresponding to the initiator bus, regardless of the state of the parity-error-response bit.
Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent delayed write transactions on the initiator bus, it is possible that the initiator's re-attempts of the write transaction may not match the original queued delayed write information contained in the delayed transaction queue. In this case, a master timeout condition may occur, possibly resulting in a system error (P_SERR# assertion). For downstream transactions, when PI7C7300A is delivering data to the target on the secondary bus and S_PERR# is asserted by the target, the following events occur: ! PI7C7300A sets the secondary interface data parity detected bit in the secondary status register, if the secondary parity error response bit is set in the bridge control register. PI7C7300A captures the parity error condition to forward it back to the initiator on the primary bus.
!
Similarly, for upstream transactions, when PI7C7300A is delivering data to the target on the primary bus and P_PERR# is asserted by the target, the following events occur: ! PI7C7300A sets the primary interface data-parity-detected bit in the status register, if the primary parity-error-response bit is set in the command register. PI7C7300A captures the parity error condition to forward it back to the initiator on the secondary bus.
!
A delayed write transaction is completed on the initiator bus when the initiator repeats the write transaction with the same address, command, data, and byte enable bits as the delayed write command that is at the head of the posted data queue. Note that the parity bit is not compared when determining whether the transaction matches those in the delayed transaction queues. Two cases must be considered: ! ! When parity error is detected on the initiator bus on a subsequent re-attempt of the transaction and was not detected on the target bus When parity error is forwarded back from the target bus
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION For downstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7300A has write status to return, the following events occur: ! ! ! PI7C7300A first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the primary interface parity-error-response bit is set in the command register. PI7C7300A sets the primary interface parity-error-detected bit in the status register. Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7300A has write status to return, the following events occur: ! PI7C7300A first asserts S1_TRDY# or S2_TRDY# and then asserts S_PERR# two cycles later, if the secondary interface parity-error-response bit is set in the bridge control register (offset 3Ch). PI7C7300A sets the secondary interface parity-error-detected bit in the secondary status register. Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue.
! !
For downstream transactions, where the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: ! PI7C7300A asserts P_PERR# two cycles after the data transfer, if the following are both true: ! The parity-error-response bit is set in the command register of the primary interface. The parity-error-response bit is set in the bridge control register of the secondary interface.
PI7C7300A completes the transaction normally.
For upstream transactions, when the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: ! PI7C7300A asserts S_PERR# two cycles after the data transfer, if the following are both true: ! The parity error response bit is set in the command register of the primary interface. The parity error response bit is set in the bridge control register of the secondary interface.
PI7C7300A completes the transaction normally.
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7.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C7300A responds as a target, it detects a data parity error on the initiator (primary) bus and the following events occur: ! ! ! ! PI7C7300A asserts P_PERR# two cycles after the data transfer, if the parity error response bit is set in the command register of primary interface. PI7C7300A sets the parity error detected bit in the status register of the primary interface. PI7C7300A captures and forwards the bad parity condition to the secondary bus. PI7C7300A completes the transaction normally.
Similarly, during upstream posted write transactions, when PI7C7300A responds as a target, it detects a data parity error on the initiator (secondary) bus, the following events occur: ! ! ! ! PI7C7300A asserts S_PERR# two cycles after the data transfer, if the parity error response bit is set in the bridge control register of the secondary interface. PI7C7300A sets the parity error detected bit in the status register of the secondary interface. PI7C7300A captures and forwards the bad parity condition to the primary bus. PI7C7300A completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target (secondary) bus by the target's assertion of S_PERR#, the following events occur: ! PI7C7300A sets the data parity detected bit in the status register of secondary interface, if the parity error response bit is set in the bridge control register of the secondary interface. PI7C7300A asserts P_SERR# and sets the signaled system error bit in the status register, if all the following conditions are met: The SERR# enable bit is set in the command register. The posted write parity error bit of P_SERR# event disable register is not set. The parity error response bit is set in the bridge control register of the secondary interface. The parity error response bit is set in the command register of the primary interface. PI7C7300A has not detected the parity error on the primary (initiator) bus which the parity error is not forwarded from the primary bus to the secondary bus.
!
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION During upstream write transactions, when a data parity error is reported on the target (primary) bus by the target's assertion of P_PERR#, the following events occur: ! ! PI7C7300A sets the data parity detected bit in the status register, if the parity error response bit is set in the command register of the primary interface. PI7C7300A asserts P_SERR# and sets the signaled system error bit in the status register, if all the following conditions are met: The SERR# enable bit is set in the command register. The parity error response bit is set in the bridge control register of the secondary interface. The parity error response bit is set in the command register of the primary interface. PI7C7300A has not detected the parity error on the secondary (initiator) bus which the parity error is not forwarded from the secondary bus to the primary bus.
Assertion of P_SERR# is used to signal the parity error condition when the initiator does not know that the error occurred. Because the data has already been delivered with no errors, there is no other way to signal this information back to the initiator. If the parity error has forwarded from the initiating bus to the target bus, P_SERR# will not be asserted.
7.3
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of PI7C7300A to data parity errors are presented according to the type of transaction in progress. This section organizes the responses of PI7C7300A to data parity errors according to the status bits that PI7C7300A sets and the signals that it asserts. Table 7-1 shows setting the detected parity error bit in the status register, corresponding to the primary interface. This bit is set when PI7C7300A detects a parity error on the primary interface. Table 7-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT
Primary Detected Parity Error Bit 0 0 1 0 1 0 0 0 1 0 0 Transaction Type Direction Bus Where Error Was Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Primary/ Secondary Parity Error Response Bits x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream
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Primary Detected Parity Error Bit 0 X = don't care Transaction Type Direction Bus Where Error Was Detected Secondary Primary/ Secondary Parity Error Response Bits x/x
Delayed Write
Upstream
Table 7-2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when PI7C7300A detects a parity error on the secondary interface. Table 7-2 SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT
Secondary Detected Parity Error Bit 0 1 0 0 0 0 0 1 0 0 0 1 X = don't care Transaction Type Direction Bus Where Error Was Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary/ Secondary Parity Error Response Bits x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Table 7-3 shows setting data parity detected bit in the primary interface's status register. This bit is set under the following conditions: ! PI7C7300A must be a master on the primary bus. ! ! The parity error response bit in the command register, corresponding to the primary interface, must be set. The P_PERR# signal is detected asserted or a parity error is detected on the primary bus.
Table 7-3 SETTING PRIMARY INTERFACE DATA PARITY ERROR DETECTED BIT
Primary Data Parity Bit 0 0 1 0 0 0 1 0 0 0 1 0 X = don't care Transaction Type Direction Bus Where Error Was Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary / Secondary Parity Error Response Bits x/x x/x 1/x x/x x/x x/x 1/x x/x x/x x/x 1/x x/x
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Table 7-4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions: ! ! ! The PI7C7300A must be a master on the secondary bus. The parity error response bit must be set in the bridge control register of secondary interface. The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus.
Table 7-4 SETTING SECONDARY INTERFACE DATA PARITY ERROR DETECTED BIT
Secondary Detected Parity Detected Bit 0 1 0 0 0 1 0 0 0 1 0 0 X= don't care Transaction Type Direction Bus Where Error Was Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary / Secondary Parity Error Response Bits x/x x/1 x/x x/x x/x x/1 x/x x/x x/x x/1 x/x x/x
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Table 7-5 shows assertion of P_PERR#. This signal is set under the following conditions: ! ! ! PI7C7300A is either the target of a write transaction or the initiator of a read transaction on the primary bus. The parity-error-response bit must be set in the command register of primary interface. PI7C7300A detects a data parity error on the primary bus or detects S_PERR# asserted during the completion phase of a downstream delayed write transaction on the target (secondary) bus.
Table 7-5 ASSERTION OF P_PERR#
P_PERR# Transaction Type Direction Bus Where Error Was Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Primary/ Secondary Parity Error Response Bits x/x x/x 1/x x/x 1/x x/x x/x x/x 1/x
1 (de-asserted) 1 0 (asserted) 1 0 1 1 1 0
Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write
Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream
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02 Delayed Write Downstream Secondary 1/1 1 Delayed Write Upstream Primary x/x 1 Delayed Write Upstream Secondary x/x X = don't care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 7-6 shows assertion of S_PERR# that is set under the following conditions: ! ! ! PI7C7300A is either the target of a write transaction or the initiator of a read transaction on the secondary bus. The parity error response bit must be set in the bridge control register of secondary interface. PI7C7300A detects a data parity error on the secondary bus or detects P_PERR# asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus.
Table 7-6 ASSERTION OF S_PERR#
S_PERR# Transaction Type Direction Bus Where Error Was Detected Primary/ Secondary Parity Error Response Bits x/x x/1 x/x x/x x/x x/x x/x x/1 x/x x/x 1/1 x/1
1 (de-asserted) Read Downstream Primary 0 (asserted) Read Downstream Secondary 1 Read Upstream Primary 1 Read Upstream Secondary 1 Posted Write Downstream Primary 1 Posted Write Downstream Secondary 1 Posted Write Upstream Primary 0 Posted Write Upstream Secondary 1 Delayed Write Downstream Primary 1 Delayed Write Downstream Secondary 02 Delayed Write Upstream Primary 0 Delayed Write Upstream Secondary X = don't care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 7-7 shows assertion of P_SERR#. This signal is set under the following conditions: ! ! ! ! PI7C7300A has detected P_PERR# asserted on an upstream posted write transaction or S_PERR# asserted on a downstream posted write transaction. PI7C7300A did not detect the parity error as a target of the posted write transaction. The parity error response bit on the command register and the parity error response bit on the bridge control register must both be set. The SERR# enable bit must be set in the command register.
Table 7-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS
P_SERR# Transaction Type Direction Bus Where Error Was Detected Primary / Secondary Parity Error Response Bits
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1 (de-asserted) Read Downstream Primary x/x 1 Read Downstream Secondary x/x 1 Read Upstream Primary x/x 1 Read Upstream Secondary x/x 1 Posted Write Downstream Primary x/x 02 (asserted) Posted Write Downstream Secondary 1/1 03 Posted Write Upstream Primary 1/1 1 Posted Write Upstream Secondary x/x 1 Delayed Write Downstream Primary x/x 1 Delayed Write Downstream Secondary x/x 1 Delayed Write Upstream Primary x/x 1 Delayed Write Upstream Secondary x/x X = don't care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 3 The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
7.4
SYSTEM ERROR (SERR#) REPORTING
PI7C7300A uses the P_SERR# signal to report conditionally a number of system error conditions in addition to the special case parity error conditions described in Section 7.2.3. Whenever assertion of P_SERR# is discussed in this document, it is assumed that the following conditions apply: ! ! For PI7C7300A to assert P_SERR# for any reason, the SERR# enable bit must be set in the command register. Whenever PI7C7300A asserts P_SERR#, PI7C7300A must also set the signaled system error bit in the status register.
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C7300A asserts P_SERR# when it detects the secondary SERR# input, S_SERR#, asserted and the SERR# forward enable bit is set in the bridge control register. In addition, PI7C7300A also sets the received system error bit in the secondary status register. PI7C7300A also conditionally asserts P_SERR# for any of the following reasons: ! ! ! ! ! ! Target abort detected during posted write transaction Master abort detected during posted write transaction Posted write data discarded after 224 (default) attempts to deliver (224 target retries received) Parity error reported on target bus during posted write transaction (see previous section) Delayed write data discarded after 224 (default) attempts to deliver (224 target retries received) Delayed read data cannot be transferred from target after 224 (default) attempts (224 target retries received)
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! Master timeout on delayed transaction
The device-specific P_SERR# status register reports the reason for the assertion of P_SERR#. Most of these events have additional device-specific disable bits in the P_SERR# event disable register that make it possible to mask out P_SERR# assertion for specific events. The master timeout condition has a SERR# enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit.
8
EXCLUSIVE ACCESS
This chapter describes the use of the LOCK# signal to implement exclusive access to a target for transactions that cross PI7C7300A.
8.1
CONCURRENT LOCKS
The primary and secondary bus lock mechanisms operate concurrently except when a locked transaction crosses PI7C7300A. A primary master can lock a primary target without affecting the status of the lock on the secondary bus, and vice versa. This means that a primary master can lock a primary target at the same time that a secondary master locks a secondary target.
8.2
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C7300A
For any PCI bus, before acquiring access to the LOCK# signal and starting a series of locked transactions, the initiator must first check that both of the following conditions are met: ! ! The PCI bus must be idle. The LOCK# signal must be de-asserted.
The initiator leaves the LOCK# signal de-asserted during the address phase and asserts LOCK# one clock cycle later. Once a data transfer is completed from the target, the target lock has been achieved.
8.2.1
LOCKED TRANSACTIONS IN DOWSTREAM DIRECTION
Locked transactions can cross PI7C7300A only in the downstream direction, from the primary bus to the secondary bus. When the target resides on another PCI bus, the master must acquire not only the lock on its own PCI bus but also the lock on every bus between its bus and the target's bus. When PI7C7300A detects on the primary bus, an initial locked transaction intended for a target on the secondary bus, PI7C7300A samples the address, transaction type, byte enable bits, and parity, as described in Section 4.6.4. It also samples the lock signal. If there is a lock established between 2 ports or the target bus is already locked by another master, then the current lock cycle is retried without forward. Because a target retry is
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION signaled to the initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is not yet established. The first locked transaction must be a memory read transaction. Subsequent locked transactions can be memory read or memory write transactions. Posted memory write transactions that are a part of the locked transaction sequence are still posted. Memory read transactions that are a part of the locked transaction sequence are not pre-fetched. When the locked delayed memory read request is queued, PI7C7300A does not queue any more transactions until the locked sequence is finished. PI7C7300A signals a target retry to all transactions initiated subsequent to the locked read transaction that are intended for targets on the other side of PI7C7300A. PI7C7300A allows any transactions queued before the locked transaction to complete before initiating the locked transaction. When the locked delayed memory read request transaction moves to the head of the delayed transaction queue, PI7C7300A initiates the transaction as a locked read transaction by de-asserting LOCK# on the target bus during the first address phase, and by asserting LOCK# one cycle later. If LOCK# is already asserted (used by another initiator), PI7C7300A waits to request access to the secondary bus until LOCK# is deasserted when the target bus is idle. Note that the existing lock on the target bus could not have crossed PI7C7300A. Otherwise, the pending queued locked transaction would not have been queued. When PI7C7300A is able to complete a data transfer with the locked read transaction, the lock is established on the secondary bus. When the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, and byte enable bits, PI7C7300A transfers the read data back to the initiator, and the lock is then also established on the primary bus. For PI7C7300A to recognize and respond to the initiator, the initiator's subsequent attempts of the read transaction must use the locked transaction sequence (de-assert LOCK# during address phase, and assert LOCK# one cycle later). If the LOCK# sequence is not used in subsequent attempts, a master timeout condition may result. When a master timeout condition occurs, SERR# is conditionally asserted (see Section 7.4), the read data and queued read transaction are discarded, and the LOCK# signal is de-asserted on the target bus. Once the intended target has been locked, any subsequent locked transactions initiated on the initiator bus that are forwarded by PI7C7300A are driven as locked transactions on the target bus. The first transaction to establish LOCK# must be Memory Read. If the first transaction is not Memory read, the following transactions behave accordingly: - Type 0 Configuration Read/Write induces master abort - Type 1 Configuration Read/Write induces master abort - I/O Read induces master abort - I/O Write induces master abort - Memory Write induces master abort When PI7C7300A receives a target abort or a master abort in response to the delayed locked read transaction, this status is passed back to the initiator, and no locks are established on either the target or the initiator bus. PI7C7300A resumes forwarding unlocked transactions in both directions. Page 62 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
8.2.2
LOCKED TRANSACTION IN UPSTREAM DIRECTION
PI7C7300A ignores upstream lock and transactions. PI7C7300A will pass these transactions as normal transactions without lock established.
8.3
ENDING EXCLUSIVE ACCESS
After the lock has been acquired on both initiator and target buses, PI7C7300A must maintain the lock on the target bus for any subsequent locked transactions until the initiator relinquishes the lock. The only time a target-retry causes the lock to be relinquished is on the first transaction of a locked sequence. On subsequent transactions in the sequence, the target retry has no effect on the status of the lock signal. An established target lock is maintained until the initiator relinquishes the lock. PI7C7300A does not know whether the current transaction is the last one in a sequence of locked transactions until the initiator de-asserts the LOCK# signal at end of the transaction. When the last locked transaction is a delayed transaction, PI7C7300A has already completed the transaction on the target bus. In this example, as soon as PI7C7300A detects that the initiator has relinquished the LOCK# signal by sampling it in the deasserted state while FRAME# is deasserted, PI7C7300A de-asserts the LOCK# signal on the target bus as soon as possible. Because of this behavior, LOCK# may not be deasserted until several cycles after the last locked transaction has been completed on the target bus. As soon as PI7C7300A has de-asserted LOCK# to indicate the end of a sequence of locked transactions, it resumes forwarding unlocked transactions. When the last locked transaction is a posted write transaction, PI7C7300A de-asserts LOCK# on the target bus at the end of the transaction because the lock was relinquished at the end of the write transaction on the initiator bus. When PI7C7300A receives a target abort or a master abort in response to a locked delayed transaction, PI7C7300A returns a target abort or a master abort when the initiator repeats the locked transaction. The initiator must then deassert LOCK# at the end of the transaction. PI7C7300A sets the appropriate status bits, flagging the abnormal target termination condition (see Section 4.8). Normal forwarding of unlocked posted and delayed transactions is resumed. When PI7C7300A receives a target abort or a master abort in response to a locked posted write transaction, PI7C7300A cannot pass back that status to the initiator. PI7C7300A asserts SERR# on the initiator bus when a target abort or a master abort is received during a locked posted write transaction, if the SERR# enable bit is set in the command register. Signal SERR# is asserted for the master abort condition if the master abort mode bit is set in the bridge control register (see Section 7.4).
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9
PCI BUS ARBITRATION
PI7C7300A must arbitrate for use of the primary bus when forwarding upstream transactions. Also, it must arbitrate for use of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to PI7C7300A, typically on the motherboard. For the secondary PCI bus, PI7C7300A implements an internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead. This chapter describes primary and secondary bus arbitration.
9.1
PRIMARY PCI BUS ARBITRATION
PI7C7300A implements a request output pin, P_REQ#, and a grant input pin, P_GNT#, for primary PCI bus arbitration. PI7C7300A asserts P_REQ# when forwarding transactions upstream; that is, it acts as initiator on the primary PCI bus. As long as at least one pending transaction resides in the queues in the upstream direction, either posted write data or delayed transaction requests, PI7C7300A keeps P_REQ# asserted. However, if a target retry, target disconnect, or a target abort is received in response to a transaction initiated by PI7C7300A on the primary PCI bus, PI7C7300A de-asserts P_REQ# for two PCI clock cycles. For all cycles through the bridge, P_REQ# is not asserted until the transaction request has been completely queued. When P_GNT# is asserted LOW by the primary bus arbiter after PI7C7300A has asserted P_REQ#, PI7C7300A initiates a transaction on the primary bus during the next PCI clock cycle. When P_GNT# is asserted to PI7C7300A when P_REQ# is not asserted, PI7C7300A parks P_AD, P_CBE, and P_PAR by driving them to valid logic levels. When the primary bus is parked at PI7C7300A and PI7C7300A has a transaction to initiate on the primary bus, PI7C7300A starts the transaction if P_GNT# was asserted during the previous cycle.
9.2
SECONDARY PCI BUS ARBITRATION
PI7C7300A implements an internal secondary PCI bus arbiter. This arbiter supports eight external masters on secondary 1 and seven external masters on secondary 2 in addition to PI7C7300A. The internal arbiter can be disabled, and an external arbiter can be used instead for secondary bus arbitration.
9.2.1
SECONDARY BUSARBITRATION USING THE INTERNAL ARBITER
To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN#, must be tied LOW. PI7C7300A has eight/seven secondary bus 1/2 request input pins, S1_REQ#[7:0], S2_REQ#[6:0], and has eight/seven secondary bus 1/2 output grant pins, S1_GNT#[7:0], S2_GNT#[6:0], to support external secondary bus masters. The secondary bus request and grant signals are connected internally to the arbiter and are not brought out to external pins when S_CFN# is HIGH. The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set taking care of 8 requests/ grants. Each set of masters can be assigned to a high Page 64 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION priority group and a low priority group. The low priority group as a whole represents one entry in the high priority group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions the highest priority is assigned to the low priority group. Priority rotates evenly among the low priority group. Therefore, members of the high priority group can be serviced n transactions out of n+1, while one member of the low priority group is serviced once every n+1 transactions. Error! Reference source not found. shows an example of an internal arbiter where four masters, including PI7C7300A, are in the high priority group, and five masters are in the low priority group. Using this example, if all requests are always asserted, the highest priority rotates among the masters in the following fashion (high priority members are given in italics, low priority members, in boldface type): B, m0, m1, m2, m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6, B, m0, m1, m2, m7 and so on. Figure 9-1 SECONDARY ARBITER EXAMPLE
Each bus master, including PI7C7300A, can be configured to be in either the low priority group or the high priority group by setting the corresponding priority bit in the arbitercontrol register. The arbiter-control register is located at offset 40h. Each master has a corresponding bit. If the bit is set to 1, the master is assigned to the high priority group. If the bit is set to 0, the master is assigned to the low priority group. If all the masters are assigned to one group, the algorithm defaults to a straight rotating priority among all the masters. After reset, all external masters are assigned to the low priority group, and PI7C7300A is assigned to the high priority group. PI7C7300A receives highest priority on the target bus every other transaction, and priority rotates evenly among the other masters. Priorities are re-evaluated every time S1_FRAME# or S2_FRAME# is asserted at the start of each new transaction on the secondary PCI bus. From this point until the time that the next transaction starts, the arbiter asserts the grant signal corresponding to the highest priority request that is asserted. If a grant for a particular request is asserted, and a higher priority request subsequently asserts, the arbiter de-asserts the asserted grant signal and asserts the grant corresponding to the new higher priority request on the next PCI clock cycle. When priorities are re-evaluated, the highest priority is assigned to the next highest priority master relative to the master that initiated the previous transaction. The master that initiated the last transaction now has the lowest priority in its group. If PI7C7300A detects that an initiator has failed to assert S1_FRAME# or S2_FRAME# after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter deasserts the grant. That master does not receive any more grants until it deasserts its request for at least one PCI clock cycle. To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant signal in the same PCI cycle in which it deasserts another. It de-asserts one grant Page 65 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION and asserts the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is busy, that is, either S1_FRAME# (S2_FRAME#) or S1_IRDY# (S2_IRDY#) is asserted, the arbiter can de-assert one grant and assert another grant during the same PCI clock cycle.
9.2.2
PREEMPTION
Preemption can be programmed to be either on or off, with the default to on (offset 4Ch, bit 31=0). Time-to-preempt can be programmed to 8,16, 32, 64, or 128 (default is 32) clocks. If the current master occupies the bus and other masters are waiting, the current master will be preempted by removing its grant (GNT#) after the next master waits for the timeto-preempt.
9.2.3
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER
The internal arbiter is disabled when the secondary bus central function control pin, S_CFN#, is tied high. An external arbiter must then be used. When S_CFN# is tied high, PI7C7300A, reconfigures four pins (two per port) to be external request and grant pins. The S1_GNT#[0] and S2_GNT#[0] pins are reconfigured to be the external request pins because they are output. The S1_REQ#[0] and S2_REQ#[0] pins are reconfigured to be the external grant pins because they are input. When an external arbiter is used, PI7C7300A uses the S1_GNT#[0] or S2_GNT#[0] pin to request the secondary bus. When the reconfigured S1_REQ#[0] and S2_REQ#[0] pin is asserted low after PI7C7300A has asserted S1_GNT#[0] or S2_GNT#[0]. PI7C7300A initiates a transaction on the secondary bus one cycle later. If grant is asserted and PI7C7300A has not asserted the request, PI7C7300A parks AD, CBE and PAR pins by driving them to valid logic levels. The unused secondary bus grants outputs, S_GNT#[7:1] and S_GNT#[6:1] are driven high. The unused secondary bus requests inputs, S1_REQ#[7:1] and S2_REQ#[6:1], should be pulled high.
9.2.4
BUS PARKING
Bus parking refers to driving the AD[31:0], CBE[3:0]#, and PAR lines to a known value while the bus is idle. In general, the device implementing the bus arbiter is responsible for parking the bus or assigning another device to park the bus. A device parks the bus when the bus is idle, its bus grant is asserted, and the device's request is not asserted. The AD and CBE signals should be driven first, with the PAR signal driven one cycle later. PI7C7300A parks the primary bus only when P_GNT# is asserted, P_REQ# is deasserted, and the primary PCI bus is idle. When P_GNT# is de-asserted, PI7C7300A 3states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C7300A is parking the primary PCI bus and wants to initiate a transaction on that bus, then PI7C7300A can start the transaction on the next PCI clock cycle by asserting P_FRAME# if P_GNT# is still asserted.
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the PCI bus. That is, PI7C7300A keeps the secondary bus grant asserted to a particular master until a new secondary bus request comes along. After reset, PI7C7300A parks the secondary bus at itself until transactions start occurring on the secondary bus. If the internal arbiter is disabled, PI7C7300A parks the secondary bus only when the reconfigured grant signal, S_REQ#[0], is asserted and the secondary bus is idle.
10
COMPACT PCI HOT SWAP
Compact PCI (cPCI) Hot Swap (PICMG 2.1, R1.0) defines a process for installing and removing PCI boards form a Compact PCI system without powering down the system. The PI7C7300A is Hot Swap Friendly silicon that supports all the cPCI Hot Swap Capable features and adds support for Software Connection Control. Being Hot Swap Friendly, the PI7C7300A supports the following: ! ! ! ! ! ! Compliance with PCI Specification 2.2 Tolerates VCC from Early Power Asynchronous Reset Tolerates Precharge Voltage I/O Buffers Meet Modified V/I Requirements Limited I/O Pin Leakage at Precharge Voltage
When the PI7C7300A resides on the Compact PCI add-in card, the Primary Bus must be the bus that is inserted into the Compact PCI system. To perform the Hot Swap function, the device must be configured according to the CPCI Hot-Swap Specifications. For the PI7C7300A, the only path for configuration is through the Primary Bus. The bridge may not be configured through either secondary buses. If the user chooses to use the secondary buses for insertion, an external register needs to be provided for the Hot Swap Control Status Register.
11
CLOCKS
This chapter provides information about the clocks.
11.1
PRIMARY CLOCK INPUTS
PI7C7300A implements a primary clock input for the PCI interface. The primary interface is synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized to the secondary clock. The secondary clock is derived internally from the primary clock, P_CLK, through an internal PLL. PI7C7300A operates at a maximum frequency of 66 MHz.
11.2
SECONDARY CLOCK OUTPUTS
PI7C7300A has 16 secondary clock outputs, S_CLKOUT[15:0] that can be used as clock inputs for up to fifteen external secondary bus devices. The S_CLKOUT[15:0] outputs Page 67 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION are derived from P_CLK. The secondary clock edges are delayed from P_CLK edges by a minimum of 0ns. This is the rule for using secondary clocks: ! Each secondary clock output is limited to no more than one load.
12
RESET
This chapter describes the primary interface, secondary interface, and chip reset mechanisms.
12.1
PRIMARY INTERFACE RESET
PI7C7300A has a reset input, P_RESET#. When P_RESET# is asserted, the following events occur: ! ! ! PI7C7300A immediately 3-states all primary and secondary PCI interface signals. PI7C7300A performs a chip reset. Registers that have default values are reset.
P_RESET# asserting and de-asserting edges can be asynchronous to P_CLK and S_CLK. PI7C7300A is not accessible during P_RESET#. After P_RESET# is deasserted, PI7C7300A remains inaccessible for 225 PCI clocks (Trhfa, page 128 of the PCI Local Bus Specification Rev 2.2) before the first configuration transaction can be accepted.
12.2
SECONDARY INTERFACE RESET
PI7C7300A is responsible for driving the secondary bus reset signals, S1_RESET# and S2_RESET#. PI7C7300A asserts S1_RESET# or S2_RESET# when any of the following conditions is met: ! Signal P_RESET# is asserted. Signal S1_RESET# or S2_RESET# remains asserted as long as P_RESET# is asserted and does not de-assert until P_RESET# is de-asserted. The secondary reset bit in the bridge control register is set. Signal S1_RESET# or S2_RESET# remains asserted until a configuration write operation clears the secondary reset bit. S1_RESET# or S2_RESET# pin is asserted. When S1_RESET# or S2_RESET# is asserted, PI7C7300A immediately 3-states all the secondary PCI interface signals associated with the Secondary S1 or S2 port. The S1_RESET# or S2_RESET# in asserting and de-asserting edges can be asynchronous to P_CLK.
!
!
When S1_RESET# or S2_RESET# is asserted, all secondary PCI interface control signals, including the secondary grant outputs, are immediately 3-stated. Signals S1_AD, S1_CBE[3:0]#, S1_PAR (S2_AD, S2_CBE[3:0]#, S2_PAR) are driven low for the Page 68 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION duration of S1_RESET# (S2_RESET#) assertion. All posted write and delayed transaction data buffers are reset. Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded. When S1_RESET# or S2_RESET# is asserted by means of the secondary reset bit, PI7C7300A remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface.
13
SUPPORTED COMMANDS
The PCI command set is given below for the primary and secondary interfaces.
13.1
PRIMARY INTERFACE
P_CBE [3:0] # 0000 0001 0010 Command Interrupt Acknowledge Special Cycle I/O Read Action Ignore Do not claim. Ignore. 1. If address is within pass through I/O range, claim and pass through. 2. Otherwise, do not pass through and do not claim for internal access. Same as I/O Read. --------1. If address is within pass through memory range, claim and pass through. 2. If address is within pass through memory mapped I/O range, claim and pass through. 3. Otherwise, do not pass through and do not claim for internal access. Same as Memory Read. --------I. Type 0 Configuration Read: If the bridge's IDSEL line is asserted, perform function decode and claim if target function is implemented. Otherwise, ignore. If claimed, permit access to target function's configuration registers. Do not pass through under any circumstances. II. Type 1 Configuration Read: 1. If the target bus is the bridge's secondary bus: claim and pass through as a Type 0 Configuration Read. 2. If the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through as a Type 1 Configuration Read. 3. Otherwise, ignore. I. Type 0 Configuration Write: same as Configuration Read. II. Type 1 Configuration Write (not special cycle request): 1. If the target bus is the bridge's secondary bus: claim and pass through as a Type 0 Configuration Write 2. If the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through unchanged as a Type 1 Configuration Write. 3. Otherwise, ignore. III. Configuration Write as Special Cycle Request
0011 0100 0101 0110
I/O Write Reserved Reserved Memory Read
0111 1000 1001 1010
Memory Write Reserved Reserved Configuration Read
1011
Configuration Write
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P_CBE [3:0] # Command Action (device = 1Fh, function = 7h) If the target bus is the bridges secondary bus: claim and pass through as a special cycle. 2. If the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through unchanged as a type 1 Configuration Write. 3. Otherwise ignore Same as Memory Read 1. Supported Same as Memory Read Same as Memory Read
1100 1101 1110 1111
Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate
13.2
SECONDARY INTERFACE
S1_CBE [3:0] # S2_CBE [3:0] # 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Command Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Action Ignore Do not claim. Ignore. Same as Primary Interface Same as I/O Read. --------Same as Primary Interface Same as Memory Read. --------Ignore I. Type 0 Configuration Write: Ignore II. Type 1 Configuration Write (not special cycle request):Ignore III. Configuration Write as Special Cycle Request (device = 1Fh, function = 7h): 1. If the target bus is the bridge's primary bus: claim and pass through as a Special Cycle 2. If the target bus is neither the primary bus nor is it in range of buses defined by the bridge's secondary and subordinate bus registers: claim and pass through unchanged as a Type 1 Configuration Write. 3. If the target bus is not the bridge's primary bus, but is in range of buses defined by the bridge's secondary and subordinate bus registers: ignore. Same as Memory Read Supported Same as Memory Read Same as Memory Read
1100 1101 1110 1111
Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate
14
CONFIGURATION REGISTERS
As PI7C7300A supports two secondary interfaces, it has two sets of configuration registers that are almost identical and accessed through different function numbers. PCI configuration defines a 64-byte space (configuration header) to define various attributes of the PCI-to-PCI Bridge as shown below. There are two configuration registers: Configuration Register 1 and Configuration Register 2 corresponding to Secondary Bus Page 70 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 1 and Secondary Bus 2 interfaces respectively. The configuration for the Primary interface is implemented through Configuration Register 1.
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14.1
CONFIGURATION REGISTER 1 AND 2
31-24 Device ID Status Reserved Class Code Header Type 23-16 15-8 Vendor ID Command 7-0 Address 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h-AFh B0h B4h-BFh C0h D0h-FFh
Revision ID Primary Latency Timer Cache Line Size Reserved Reserved Secondary Latency Subordinate Bus Secondary Bus Primary Bus Number Timer Number Number Secondary Status I/O Limit I/O Base Memory Limit Memory Base Prefetchable Memory Limit Prefetchable Memory Base Prefetchable Base Upper 32-bit Prefetchable Limit Upper 32-bit I/O Limit Upper 16-bit I/O Base Upper 16-bit Reserved ECP Pointer Reserved Bridge Control Reserved Arbiter Control Diagnostic / Chip Control Reserved Upstream Memory Control Reserved Hot Swap Switch Time Slot Upstream (S1 or S2 to P) Memory Limit Upstream (S1 or S2 to P) Memory Base Upstream (S1 or S2 to P) Memory Base Upper 32-bit Upstream (S1 or S2 to P) Memory Limit Upper 32-bit Reserved Reserved Reserved P_SERR# Event Disable Reserved Secondary Clock Control Reserved Reserved Master Timeout Counter Port Option Retry Counter Sampling Timer Secondary Successful I/O Read Counter Secondary Successful I/O Write Counter Secondary Successful Memory Read Counter Secondary Successful Memory Write Counter Primary Successful I/O Read Counter Primary Successful I/O Write Counter Primary Successful Memory Read Counter Primary Successful Memory Write Counter Reserved Chassis Number Slot Number Next Pointer Capability ID Reserved Hot Swap Control and Status Next Pointer Capability ID Reserved
14.1.1
VENDOR ID REGISTER - OFFSET 00h
Bit 15:0 Function Vendor ID Type R/O Description Identifies Pericom as vendor of this device. Hardwired as 12D8h.
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14.1.2
DEVICE ID REGISTER - OFFSET 00h
Configuration Register 1
Bit 31:16 Function Device ID Type R/O Description Identifies this device as the PI7C7300A. Hardwired as 71E2h.
Configuration Register 2
Bit 31:16 Function Device ID Type R/O Description Identifies this device as the PI7C7300A. Hardwired as 71E3h.
14.1.3
COMMAND REGISTER - OFFSET 04h
Bit Function Type Description Controls response to I/O access on the primary interface 0: ignore I/O transactions on the primary interface 0 I/O Space Enable R/W 1: enable response to I/O transactions on the primary interface Reset to 0 Controls response to memory accesses on the primary interface 1 Memory Space Enable 0: ignore memory transactions on the primary interface R/W 1: enable response to memory transactions on the primary interface Reset to 0 Controls ability to operate as a bus master on the primary interface 0: do not initiate memory or I/O transactions on the primary interface and disable response to memory and I/O transactions on secondary 1 interface R/W 1: enables PI7C7300A to operate as a master on the primary interfaces for memory and I/O transactions forwarded from the secondary interface Reset to 0 No special cycles defined. Bit is defined as read only and returns 0 when read Memory write and invalidate not supported. Bit is implemented as read only and returns 0 when read (unless forwarding a transaction for another master) Controls response to VGA compatible palette accesses 0: ignore VGA palette accesses on the primary 5 VGA Palette Snoop Enable R/W 1: enable positive decoding response to VGA palette writes on the primary interface with I/O address bits AD[9:0] equal to 3C6h, 3C8h, and 3C9h (inclusive of ISA alias; AD[15:10] are not decoded and may be any value)
2
Bus Master Enable
3 4
Special Cycle Enable Memory Write And Invalidate Enable
R/O R/O
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Bit Function Type Description Controls response to parity errors 0: PI7C7300A may ignore any parity errors that it detects and continue normal operation R/W 1: PI7C7300A must take its normal action when a parity error is detected Reset to 0 Controls the ability to perform address / data stepping 7 Wait Cycle Control 0: disable address/data stepping (affects primary and secondary) R/O 1: enable address/data stepping (affects primary and secondary) Reset to 0 Controls the enable for the P_SERR# pin 0: disable the P_SERR# driver 8 P_SERR# enable R/W 1: enable the P_SERR# driver Reset to 0 Controls PI7C7300A's ability to generate fast back-to-back transactions to different devices on the primary interface. 9 Fast Back-toBack Enable R/W 0: no fast back-to-back transactions 1: enable fast back-to-back transactions Reset to 0 Returns 000000 when read
6
Parity Error Response
15:10
Reserved
R/O
14.1.4
STATUS REGISTER - OFFSET 04h
Bit 19:16 20 Function Reserved Capabilities List Type R/O R/O Description Reset to 0 Set to 1 to enable support for the capability list (offset 34h is the pointer to the data structure) Reset to 1 Set to 1 to enable 66MHz operation on the primary interface Reset to 1 Reset to 0 Set to 1 to enable decoding of fast back-to-back transactions on the primary interface to different targets Reset to 1 Set to 1 when P_PERR# is asserted and bit 6 of command register is set Reset to 0 DEVSEL# timing (medium decoding) 00: fast DEVSEL# decoding 01: medium DEVSEL# decoding 10: slow DEVSEL# decoding 11: reserved Reset to 01
21
66MHz Capable
R/O
22 23
Reserved Fast Back-toBack Capable
R/O R/O
24
Data Parity Error Detected
R/WC
26:25
DEVSEL# timing
R/O
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Bit 27 Function Signaled Target Abort Received Target Abort Type R/WC Description Set to 1 (by a target device) whenever a target abort cycle occurs Reset to 0 Set to 1 (by a master device) whenever transactions are terminated with target aborts Reset to 0 Set to 1 (by a master) when transactions are terminated with Master Abort Reset to 0 Set to 1 when P_SERR# is asserted Reset to 0 Set to 1 when address or data parity error is detected on the primary interface Reset to 0
28
R/WC
29
Received Master Abort
R/WC
30
Signaled System Error Detected Parity Error
R/WC
31
R/WC
14.1.5
REVISION ID REGISTER - OFFSET 08h
Bit 7:0 Function Revision Type R/O Description Indicates revision number of device. Hardwired to 00h
14.1.6
CLASS CODE REGISTER - OFFEST 08h
Bit 15:8 23:16 31:24 Function Programming Interface Sub-Class Code Base Class Code Type R/O R/O R/O Description Read as 0 to indicate no programming interfaces have been defined for PCI-to-PCI bridges Read as 04h to indicate device is PCI-to-PCI bridge Read as 06h to indicate device is a bridge device
14.1.7
CACHE LINE SIZE REGISTER - OFFSET 0Ch
Bit 7:0 Function Cache Line Size Type R/W Description Designates the cache line size for the system and is used when terminating memory write and invalidate transactions and when prefetching memory read transactions. Only cache line sizes (in units of 4-byte) which are a power of two are valid (only one bit can be set in this register; only 00h, 01h, 02h, 04h, 08h, and 10h are valid values). Reset to 0
14.1.8
PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch
Bit 15:8 Function Primary Latency timer Type R/W Description This register sets the value for the Master Latency Timer which starts counting when the master asserts FRAME#. Reset to 0
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14.1.9
HEADER TYPE REGISTER - OFFSET 0Ch
Configuration Register 1
Bit 23:16 Function Header Type Type R/O Description Read as 81h to designate function 0 (multiple function PCI-to-PCI bridge for secondary bus S1)
Configuration Register 2
Bit 23:16 Function Header Type Type R/O Description Read as 01h to designate function 1 (single function PCI-to-PCI bridge for secondary bus S2)
14.1.10
PRIMARY BUS NUMBER REGISTER - OFFSET 18h
Bit 7:0 Function Primary Bus Number Type R/W Description Indicates the number of the PCI bus to which the primary interface is connected. The value is set in software during configuration. Reset to 0
14.1.11
SECONDARY (S1 or S2) BUS NUMBER REGISTER - OFFSET 18h
Bit 15:8 Function Secondary (S1 or S2) Bus Number Type R/W Description Indicates the number of the PCI bus to which the secondary interface (S1 or S2) is connected. The value is set in software during configuration. Reset to 0
14.1.12
SUBORDINATE (S1 or S2) BUS NUMBER REGISTER - OFFSET 18h
Bit 23:16 Function Subordinate (S1 or S2) Bus Number Type R/W Description Indicates the number of the PCI bus with the highest number that is subordinate to the bridge. The value is set in software during configuration. Reset to 0
14.1.13
SECONDARY LATENCY TIMER REGISTER - OFFSET 18h
Bit 31:24 Function Secondary Latency Timer Type R/W Description Designated in units of PCI bus clocks. Latency timer checks for master accesses on the secondary bus interfaces that remain unclaimed by any target. Reset to 0
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14.1.14
I/O BASE REGISTER - OFFSET 1Ch
Bit 3:0 7:4 Function 32-bit Indicator I/O Base Address [15:12] Type R/O R/W Description Read as 01h to indicate 32-bit I/O addressing Defines the bottom address of the I/O address range for the bridge to determine when to forward I/O transactions from one interface to the other. The upper 4 bits correspond to address bits [15:12] and are writable. The lower 12 bits corresponding to address bits [11:0] are assumed to be 0. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O base address upper 16 bits address register Reset to 0
14.1.15
I/O LIMIT REGISTER - OFFSET 1Ch
Bit 11:8 15:12 Function 32-bit Indicator I/O Base Address [15:12] Type R/O R/W Description Read as 01h to indicate 32-bit I/O addressing Defines the top address of the I/O address range for the bridge to determine when to forward I/O transactions from one interface to the other. The upper 4 bits correspond to address bits [15:12] and are writable. The lower 12 bits corresponding to address bits [11:0] are assumed to be FFFh. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O base address upper 16 bits address register Reset to 0
14.1.16
SECONDARY STATUS REGISTER - OFFSET 1Ch
Bit 20:16 21 Function Reserved 66MHz Capable Type R/O R/O Description Reset to 0 Set to 1 to enable 66MHz operation on the secondary (S1 or S2) interface Reset to 1 Reset to 0 Set to 1 to enable decoding of fast back-to-back transactions on the secondary (S1 or S2) interface to different targets Reset to 0 Set to 1 when S1_PERR# or S2_PERR# is asserted and bit 6 of command register is set Reset to 0 DEVSEL# timing (medium decoding) DEVSEL# timing 00: fast DEVSEL# decoding 01: medium DEVSEL# decoding 10: slow DEVSEL# decoding 11: reserved Reset to 01 Set to 1 (by a target device) whenever a target abort cycle occurs on its secondary (S1 or S2) interface Reset to 0
22 23
Reserved Fast Back-toBack Capable
R/O R/O
24
Data Parity Error Detected
R/WC
26:25
R/O
27
Signaled Target Abort
R/WC
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Bit 28 Function Received Target Abort Type R/WC Description Set to 1 (by a master device) whenever transactions on its secondary (S1 or S2) interface are terminated with target abort Reset to 0 Set to 1 (by a master) when transactions on its secondary (S1 or S2) interface are terminated with Master Abort Reset to 0 Set to 1 when S1_SERR# or S2_SERR# is asserted R/WC Reset to 0 Set to 1 when address or data parity error is detected on the secondary (S1 or S2) interface Reset to 0
29
Received Master Abort Received System Error Detected Parity Error
R/WC
30
31
R/WC
14.1.17
MEMORY BASE REGISTER - OFFSET 20h
Bit 3:0 Function Type R/O Description Lower four bits of register are read only and return 0. Reset to 0 Defines the bottom address of an address range for the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits corresponding to address bits [19:0] are assumed to be 0. Reset to 0
15:4
Memory Base Address [15:4]
R/W
14.1.18
MEMORY LIMIT REGISTER - OFFSET 20h
Bit 19:16 Function Type R/O Description Lower four bits of register are read only and return 0. Reset to 0 Defines the top address of an address range for the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits corresponding to address bits [19:0] are assumed to be FFFFFh.
31:20
Memory Limit Address [31:20]
R/W
14.1.19
PREFETCHABLE MEMORY BASE REGISTER - OFFSET 24h
Bit 3:0 Function 64-bit addressing Type R/O Description Indicates 64-bit addressing 0000: 32-bit addressing 0001: 64-bit addressing Reset to 1
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15:4 Prefetchable Memory Base Address [31:20] R/W Defines the bottom address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits are assumed to be 0.
14.1.20
PREFETCHABLE MEMORY LIMIT REGISTER - OFFSET 24h
Bit 19:16 Function 64-bit addressing Type R/O Description Indicates 64-bit addressing 0000: 32-bit addressing 0001: 64-bit addressing Reset to 1 Defines the top address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits are assumed to be FFFFFh.
31:20
Prefetchable Memory Base Address [31:20]
R/W
14.1.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER - OFFSET 28h
Bit 31:0 Function Prefetchable Memory Base Address, Upper 32-bits [63:32] Type R/W Description Defines the upper 32-bits of a 64-bit bottom address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. Reset to 0
14.1.22
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER - OFFSET 2Ch
Bit 31:0 Function Prefetchable Memory Limit Address, Upper 32-bits [63:32] Type R/W Description Defines the upper 32-bits of a 64-bit top address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. Reset to 0
14.1.23
I/O BASE ADDRESS UPPER 16-BITS REGISTER - Offset 30h
Bit 15:0 Function I/O Base Address, Upper 16-bits [31:16] Type R/W Description Defines the upper 16-bits of a 32-bit bottom address of an address range for the bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0
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14.1.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER - OFFSET 30h
Bit 31:0 Function I/O Limit Address, Upper 16-bits [31:16] Type R/W Description Defines the upper 16-bits of a 32-bit top address of an address range for the bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0
14.1.25
ECP POINTER REGISTER - OFFSET 34h
Bit 7:0 Function Enhanced Capabilities Port Pointer Type R/O Description Enhanced capabilities port offset pointer. Read as B0h to indicate that the first item resides at that configuration offset.
14.1.26
BRIDGE CONTROL REGISTER - OFFSET 3Ch
Bit 16 Function Parity Error Response Type R/W Description Controls the bridge's response to parity errors on the secondary interface. 0: ignore address and data parity errors on the secondary interface 1: enable parity error reporting and detection on the secondary interface Reset to 0 Controls the forwarding of S1_SERR# or S2_SERR# to the primary interface. 0: disable the forwarding of S1_SERR# or S2_SERR# to primary interface 1: enable the forwarding of S1_SERR# or S2_SERR# to primary interface Reset to 0 Modifies the bridge's response to ISA I/O addresses, applying only to those addresses falling within the I/O base and limit address registers and within the first 64KB or PCI I/O space. 0: forward all I/O addresses in the range defined by the I/O base and I/O limit registers 1: blocks forwarding of ISA I/O addresses in the range defined by the I/O base and I/O limit registers that are in the first 64KB of I/O space that address the last 768 bytes in each 1KB block. Secondary I/O transactions are forwarded upstream if the address falls within the last 768 bytes in each 1KB block Reset to 0
17
S1_SERR# enable
R/W
18
ISA enable
R/W
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Bit 19 Function VGA enable Type R/W Description Controls the bridge's response to VGA compatible addresses. 0: does not forward VGA compatible memory and I/O addresses from primary to secondary 1: forward VGA compatible memory and I/O addresses from primary to secondary regardless of other settings Reset to 0 Reserved. Returns 0 when read. Reset to 0 Control's bridge's behavior responding to master aborts on secondary interface. 0: does not report master aborts (returns FFFF_FFFFh on reads and discards data on writes) 1: reports master aborts by signaling target abort if possible by the assertion of P_SERR# if enabled Reset to 0 Controls the assertion of S1_RESET# or S2_RESET# signal pin on the secondary interface 0: does not force the assertion of S1_RESET# or S2_RESET# pin 1: forces the assertion of S1_RESET# or S2_RESET# Reset to 0 Controls bridge's ability to generate fast back-to-back transactions to different devices on the secondary interface. 0: does not allow fast back-to-back transactions 1: enables fast back-to-back transactions Reset to 0 Reserved. Reset to 0 Reserved. Reset to 0 This bit is set to 1 when either the primary master timeout counter or secondary master timeout counter expires. Reset to 0 This bit Is set to 1 and P_SERR# is asserted when either the primary discard timer or the secondary S1 or S2 discard timer expire. Reset to 0 Reserved. Returns 0 when read. Reset to 0.
20 21
Reserved Master Abort Mode
R/O R/W
22
Secondary Interface Reset
R/W
23
Fast Back-toBack Enable
R/W
24 25 26
Reserved Reserved Master Timeout Status
R/W R/W R/WC
27
Discard Timer P_SERR# enable
R/WC
31-28
Reserved
R/O
14.1.27
DIAGNOSTIC / CHIP CONTROL REGISTER - OFFSET 40h
Configuration 1
Bit 0 1 Function Reserved Memory Write Disconnect Control Type R/O R/W Description Reserved. Returns 0 when read. Reset to 0 Controls when the bridge (as a target) disconnects memory write transactions. 0: memory write disconnects at 4KB aligned address boundary 1: memory write disconnects at cache line aligned address boundary Reset to 0 Reserved. Returns 0 when read. Reset to 0.
3:2
Reserved
R/O
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Bit 4 Function Memory Read Flow-Through Control Type R/W Description Controls whether the bridge supports memory read flow-through 0: Enable 1: Disable Reset to 0 Reserved. Returns 0 when read. Reset to 0 Controls the testability of the bridge's internal counters. The bits are used for chip test only. 00: all bits are exercised 01: byte 1 is exercised 10: byte 2 is exercised 11: byte 3 is exercised Reset to 0 Reserved. Returns 0 when read. Reset to 0.
8:5 10:9
Reserved Test Mode For All Counters at P and S1
R/O R/O
15:11
Reserved
R/O
Configuration 2
Bit 0 1 Function Reserved Memory Write Disconnect Control at S2 Type R/O R/W Description Reserved. Returns 0 when read. Reset to 0 Controls when the bridge (as a target) disconnects memory write transactions. 0: memory write disconnects at 4KB aligned address boundary 1: memory write disconnects at cache line aligned address boundary Reset to 0 Reserved. Returns 0 when read. Reset to 0 Controls whether the bridge supports memory read flow-through 0: Enable 1: Disable Reset to 0 Reserved. Returns 0 when read. Reset to 0 Controls the testability of the bridge's internal counters. The bits are used for chip test only. 00: all bits are exercised 01: byte 1 is exercised 10: byte 2 is exercised 11: byte 3 is exercised Reset to 0 Reserved. Returns 0 when read. Reset to 0.
3:2 4
Reserved Memory Read Flow-through Control
R/O R/W
8:5 10:9
Reserved Test Mode For All Counters at S2
R/O R/O
15:11
Reserved
R/O
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14.1.28
ARBITER CONTROL REGISTER - OFFSET 40h
Bit 23:16 Function Arbiter Control Type R/W Description Each bit controls whether a secondary bus master is assigned to the high priority group or the low priority group. Bits [23:16] correspond to request inputs S1_REQ[7:0] or S2_REQ[6:0] 0: low priority 1: high priority Reset to 0 Reserved. Returns 0 when read. Reset to 0 Controls whether the S1 or S2 interface of the bridge is in the high priority group or the low priority group. 0: low priority 1: high priority Reset to 1 Controls the arbiter's park function. 0: park to last master 1: park to bridge port S1 or S2 Reset to 0 Reserved. Returns 0 when read. Reset to 0.
24 25
Reserved Priority of Secondary Interface
R/O R/W
26
Arbiter Park Function
R/W
31:27
Reserved
R/O
14.1.29
UPSTREAM MEMORY CONTROL REGISTER - OFFSET 48h
Bit Function Upstream (S1 or S2 to P) Memory Base and Limit Enable Type Description 0: Upstream memory is the entire range except the down stream memory channel 1: Upstream memory is confined to upstream Memory Base and Limit (See offset 50th and 54th for upstream memory range) Reset to 0 0: Upstream memory is prefetchable at Primary R/W 1: Upstream memory is not prefetchable at Primary Reset to 0 Reserved. Returns 0 when read. Reset to 0
16
R/W
17
Upstream (S1 or S2 to P) Memory Prefetchable Enable Reserved
31:18
R/O
14.1.30
HOT SWAP SWITCH TIME SLOT REGISTER - OFFSET 4Ch
Bit 27:0 Function Hot Swap Time Slot Type R/W Description Hot Swap time slot (15K PCI clocks) Reset to 0003A98h
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Bit Function Type Description Sets the number of clocks for time-to-preempt after another master request. 000: 32 clocks 001: 8 clocks 010: 16 clocks 011: 64 clocks 100: 128 clocks Reset to 000 Sets preemption. 31 Preemption R/W 0: preemption ON 1: preemption OFF Reset to 0
30:28
Secondary Bus Master Preemption Control
R/W
14.1.31
UPSTREAM (S1 or S2 to P) MEMORY BASE REGISTER - OFFSET 50h
Bit Function Type Description 0: 32 bit addressing 1: 64 bit addressing Reset to 1 Controls upstream memory base address. R/W Reset to 00000000h
3:0
64 bit addressing
R/O
15:4
Upstream Memory Base Address
14.1.32
UPSTREAM (S1 or S2 to P) MEMORY LIMIT REGISTER - OFFSET 50h
Bit Function Type Description 0: 32 bit addressing 1: 64 bit addressing Reset to 1 Controls upstream memory limit address. R/W Reset to 000FFFFFh
19:16
64 bit addressing
R/O
31:20
Upstream Memory Limit Address
14.1.33
UPSTREAM (S1 or S2 to P) MEMORY BASE UPPER 32-BITS REGISTER - OFFSET 54h
Bit 31:0 Function Upstream Memory Base Address Type R/W Reset to 0 Description Defines bits [63:32] of the upstream memory base
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14.1.34
UPSTREAM (S1 or S2 to P) MEMORY LIMIT UPPER 32 BITS REGISTER - OFFSET 58h
Bit 31:0 Function Upstream Memory Limit Address Type R/W Reset to 0 Description Defines bits [63:32] of the upstream memory limit
14.1.35
P_SERR# EVENT DISABLE REGISTER - OFFSET 64h
Bit 0 Function Reserved Type R/O Description Reserved. Returns 0 when read. Reset to 0 Controls PI7C7300A's ability to assert P_SERR# when it is unable to transfer any read data from the target after 224 attempts. 0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the command register is set. 1: P_SERR# is not assert if this event occurs. Reset to 0 Controls PI7C7300A's ability to assert P_SERR# when it is unable to transfer delayed write data after 224 attempts. 2 Posted Write Non-Delivery R/W 0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the command register is set 1: P_SERR# is not asserted if this event occurs Reset to 0 Controls PI7C7300A's ability to assert P_SERR# when it receives a target abort when attempting to deliver posted write data. 3 Target Abort During Posted Write R/W 0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the command register is set 1: P_SERR# is not asserted if this event occurs Reset to 0 Controls PI7C7300A's ability to assert P_SERR# when it receives a master abort when attempting to deliver posted write data. 4 Master Abort On Posted Write R/W 0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the command register is set 1: P_SERR# is not asserted if this event occurs Reset to 0 Controls PI7C7300A's ability to assert P_SERR# when it is unable to transfer delayed write data after 224 attempts. 5 Delayed Write Non-Delivery R/W 0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the command register is set 1: P_SERR# is not asserted if this event occurs Reset to 0
1
Posted Write Parity Error
R/W
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Bit Function Type Description Controls PI7C7300A's ability to assert P_SERR# when it is unable to transfer any read data from the target after 224 attempts. 0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the command register is set 1: P_SERR# is not asserted if this event occurs Reset to 0 Reserved. Returns 0 when read. Reset to 0
6
Delayed Read - No Data From Target
R/W
7
Reserved
R/O
14.1.36
SECONDARY CLOCK CONTROL REGISTER - OFFSET 68h
Configuration Register 1
Bit 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 Function Clock 0 disable Clock 1 disable Clock 2 disable Clock 3 disable Clock 4 disable Clock 5 disable Clock 6 disable Clock 7 disable Type R/W R/W R/W R/W R/W R/W R/W R/W Description If either bit is 0, then S1_CLKOUT [0] is enabled. If both bits are 1, the S1_CLKOUT [0] is disabled. If either bit is 0, then S1_CLKOUT [1] is enabled. If both bits are 1, the S1_CLKOUT [1] is disabled. If either bit is 0, then S1_CLKOUT [2] is enabled. If both bits are 1, the S1_CLKOUT [2] is disabled. If either bit is 0, then S1_CLKOUT [3] is enabled. If both bits are 1, the S1_CLKOUT [3] is disabled. If either bit is 0, then S1_CLKOUT [4] is enabled. If both bits are 1, the S1_CLKOUT [4] is disabled. If either bit is 0, then S1_CLKOUT [5] is enabled. If both bits are 1, the S1_CLKOUT [5] is disabled. If either bit is 0, then S1_CLKOUT [6] is enabled. If both bits are 1, the S1_CLKOUT [6] is disabled. If either bit is 0, then S1_CLKOUT [7] is enabled. If both bits are 1, the S1_CLKOUT [7] is disabled.
Configuration Register 2
Bit 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 Function Clock 0 disable Clock 1 disable Clock 2 disable Clock 3 disable Clock 4 disable Clock 5 disable Clock 6 disable Clock 7 disable Type R/W R/W R/W R/W R/W R/W R/W R/W Description If either bit is 0, then S2_CLKOUT [0] is enabled. If both bits are 1, the S2_CLKOUT [0] is disabled. If either bit is 0, then S2_CLKOUT [1] is enabled. If both bits are 1, the S2_CLKOUT [1] is disabled. If either bit is 0, then S2_CLKOUT [2] is enabled. If both bits are 1, the S2_CLKOUT [2] is disabled. If either bit is 0, then S2_CLKOUT [3] is enabled. If both bits are 1, the S2_CLKOUT [3] is disabled. If either bit is 0, then S2_CLKOUT [4] is enabled. If both bits are 1, the S2_CLKOUT [4] is disabled. If either bit is 0, then S2_CLKOUT [5] is enabled. If both bits are 1, the S2_CLKOUT [5] is disabled. If either bit is 0, then S2_CLKOUT [6] is enabled. If both bits are 1, the S2_CLKOUT [6] is disabled. If either bit is 0, then S2_CLKOUT [7] is enabled. If both bits are 1, the S2_CLKOUT [7] is disabled.
14.1.37
PORT OPTION REGISTER - OFFSET 74h
Bit 0 Function Reserved Type R/O Description Reserved. Returns 0 when read. Reset to 0.
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Bit Function Type Description Controls PI7C7300A's detection mechanism for matching memory read retry cycles from the initiator on the primary interface 0: exact matching for non-posted memory write retry cycles from initiator on the primary interface 1: alias MEMRL or MEMRM to MEMR for memory read retry cycles from the initiator on the primary interface Reset to 0 Controls PI7C7300A's detection mechanism for matching non-posted memory write retry cycles from the initiator on the primary interface Primary MEMW Command Alias Enable 0: exact matching for non-posted memory write retry cycles from initiator on the primary interface 1: alias MEMWI to MEMW for non-posted memory write retry cycles from initiator on the primary interface Reset to 0 Controls PI7C7300A's detection mechanism for matching memory read retry cycles from the initiator on S1 Secondary MEMR Command Alias Enable 0: exact matching for memory read retry cycles from initiator on the S1 or S2 interface 1: alias MEMRL or MEMRM to MEMR for memory read retry cycles from initiator on the S1 or S2 interface Reset to 0 Controls PI7C7300A's detection mechanism for matching non-posted memory write retry cycles from the initiator on the primary interface Secondary MEMW Command Alias Enable 0: exact matching for non-posted memory write retry cycles from initiator on the S1 or S2 interface 1: alias MEMWI to MEMW for non-posted memory write retry cycles from initiator on the S1 or S2 interface Reset to 0 Reserved. Returns 0 when read. Reset to 0. Controls PI7C7300A's ability to enable long requests for lock cycles 0: normal lock operation R/W 1: enable long request for lock cycle Reset to 0 Control's PI7C7300A's ability to enable S1 or S2 to hold requests longer. Enable Secondary To Hold Request Longer 0: internal S1 or S2 master will release REQ_L after FRAME_L assertion 1: internal S1 or S2 master will hold REQ_L until there is no transactions pending in FIFO or until terminated by target Reset to 1
1
Primary MEMR Command Alias Enable
R/W
2
R/W
3
R/W
4
R/W
8:5
Reserved
R/O
9
Enable Long Request
10
R/W
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Bit Function Type Description Control's PI7C7300A's ability to hold requests longer at the Primary Port. 0: internal Primary master will release REQ_L after FRAME_L assertion 1: internal Primary master will hold REQ_L until there is no transactions pending in FIFO or until terminated by target Reset to 1 Reserved. Returns 0 when read. Reset to 0.
11
Enable Primary To Hold Request Longer
R/W
15:12
Reserved
R/O
14.1.38
MASTER TIMEOUT COUNTER REGISTER - OFFSET 74h
Bit 31:16 Function Master Timeout Type R/W Description Holds the maximum number of PCI clocks that PI7C7300A will wait for initiator to retry the same cycle before reporting timeout. Master timeout occurs after 215 PCI clocks. Default is 8000h.
14.1.39
RETRY COUNTER REGISTER - OFFSET 78h
Bit 31:0 Function Retry Counter Type R/W Description Holds the maximum number of attempts that PI7C7300A will try before reporting retry timeout. Retry count set at 224 PCI clocks. Default is 0100 0000h.
14.1.40
SAMPLING TIMER REGISTER - OFFSET 7Ch
Bit Function Type Description Sets the duration (in PCI clocks) during which PI7C7300A will record the number of successful transactions for performance evaluation. The recording will start right after this register is programmed and will be cleared after the timer expires. Maximum period is 128 seconds at 33MHz. Reset to 0.
31:0
Sampling Timer
R/W
14.1.41
SECONDARY SUCCESSFUL I/O READ COUNTER REGISTER - OFFSET 80h
Bit 31:0 Function Successful I/O Read Counts on S1 or S2 Type R/W Description Stores the successful I/O read count on S1 or S2 and is updated when the sampling timer is active. Reset to 0
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14.1.42
SECONDARY SUCCESSFUL I/O WRITE COUNTER REGISTER - OFFSET 84h
Bit 31:0 Function Successful I/O Write Counts on S1 or S2 Type R/W Description Stores the successful I/O write count on S1 or S2 and is updated when the sampling timer is active. Reset to 0
14.1.43
SECONDARY SUCCESSFUL MEMORY READ COUNTER REGISTER - Offset 88h
Bit 31:0 Function Successful Memory Read Counts on S1 or S2 Type R/W Description Stores the successful memory read count on S1 or S2 and is updated when the sampling timer is active. Reset to 0
14.1.44
SECONDARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER - OFFSET 8Ch
Bit 31:0 Function Successful Memory Write Counts on S1 or S2 Type R/W Description Stores the successful memory write count on S1 or S2 and is updated when the sampling timer is active. Reset to 0
14.1.45
PRIMARY SUCCESSFUL I/O READ COUNTER REGISTER - OFFSET 90h
Bit 31:0 Function Successful I/O Read Counts on Primary Type R/W Description Stores the successful I/O read count on Primary and is updated when the sampling timer is active. Reset to 0
14.1.46
PRIMARY SUCCESSFUL I/O WRITE COUNTER REGISTER - OFFSET 94h
Bit 31:0 Function Successful I/O Write Counts on Primary Type R/W Description Stores the successful I/O write count on Primary and is updated when the sampling timer is active. Reset to 0
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14.1.47
PRIMARY SUCCESSFUL MEMORY READ COUNTER REGISTER - OFFSET 98h
Bit 31:0 Function Successful Memory Read Counts on Primary Type R/W Description Stores the successful memory read count on Primary and is updated when the sampling timer is active. Reset to 0
14.1.48
PRIMARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER - OFFSET 9Ch
Bit 31:0 Function Successful Memory Write Counts on Primary Type R/W Description Stores the successful memory write count on Primary and is updated when the sampling timer is active. Reset to 0
14.1.49
CAPABILITY ID REGISTER - OFFSET B0h
Bit Function Type Description Capability ID for slot identification 00h: Reserved 01h: PCI Power Management (PCIPM) 02h: Accelerated Graphics Port (AGP) 03h: Vital Product Data (VPD) 7:0 Capability ID R/O 04h: Slot Identification (SI) 05h: Message Signaled Interrupts (MSI) 06h: Compact PCI Hot Swap (CHS) 07h - 255h: Reserved Reset to 04h
14.1.50
NEXT POINTER REGISTER - OFFSET B0h
Bit 15:8 Function Next Pointer Type R/O 0000 0000: next pointer (00h if HS_EN is 0) Description Reset to 1100 0000: next pointer (C0h if HS_EN is 1)
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14.1.51
SLOT NUMBER REGISTER - OFFSET B0h
Bit 20:16 Function Expansion Slot Number First in Chassis Reserved Type R/W Reset to 0 First in chassis R/W R/O Reset to 0 Reserved. Returns 0 when read. Reset to 0. Description Determines expansion slot number
21 23:22
14.1.52
CHASSIS NUMBER REGISTER - OFFSET B0h
Bit 31:24 Function Chassis Number Register Type R/W Reset to 0 Description Chassis number register.
14.1.53
CAPABILITY ID REGISTER - OFFSET C0h
Bit Function Type Description Capability ID for Hot Swap 00h: Reserved 01h: PCI Power Management (PCIPM) 02h: Accelerated Graphics Port (AGP) 7:0 Capability ID for Hot Swap 03h: Vital Product Data (VPD) R/O 04h: Slot Identification (SI) 05h: Message Signaled Interrupts (MSI) 06h: Compact PCI Hot Swap (CHS) 07h - 255h: Reserved Reset to 06h
14.1.54
NEXT POINTER REGISTER - OFFSET C0h
Bit 15:8 Function Next Pointer Type R/O Description 00: End of pointer (00h).
14.1.55
HOT SWAP CONTROL AND STATUS REGISTER - OFFSET C0h
Bit 16 17 18 Function Not Available ENUM Signal Mask Not Available Type R/O R/W R/O 1: Enable ENUM# signal Not used. Returns 0 when read. Reset to 0 Description Not used. Returns 0 when read. Reset to 0 0: Mask ENUM# signal
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Bit Function Type Description LOO signal (LED on/off) 0: LED on 19 LED ON/OFF R/W 1: LED off Reset to 0 Not Used. Returns 0 when read. Reset to 0 0: ENUM# asserted 1: ENUM# not asserted Reset to 0 0: ENUM# asserted 23 ENUM# Status - Insertion Reserved R/W 1: ENUM# not asserted Reset to 0 Reserved. Returns 0 when read. Reset to 0
21:20
Not Available ENUM# Status - Extraction
R/O
22
R/W
31:24
R/O
15
BRIDGE BEHAVIOR
A PCI cycle is initiated by asserting the FRAME# signal. In a bridge, there are a number of possibilities. Those possibilities are summarized in the table below:
15.1
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES
Initiator Master on Primary Target Target on Primary Response PI7C7300A does not respond. It detects this situation by decoding the address as well as monitoring the P_DEVSEL# for other fast and medium devices on the Primary Port. PI7C7300A asserts P_DEVSEL#, terminates the cycle normally if it is able to be posted, otherwise return with a retry. It then passes the cycle to the appropriate port. When the cycle is complete on the target port, it will wait for the initiator to repeat the same cycle and end with normal termination. PI7C7300A does not respond and the cycle will terminate as master abort. PI7C7300A does not respond. PI7C7300A asserts S1_DEVSEL# or S2_DEVSEL#, terminates the cycle normally if it is able to be posted, otherwise returns with a retry. It then passes the cycle to the appropriate port. When cycle is complete on the target port, it will wait for the initiator to repeat the same cycle and end with normal termination. PI7C7300A does not respond.
Master on Primary
Target on Secondary
Master on Primary Master on Secondary Master on Secondary
Target not on Primary nor Secondary Port Target on the same Secondary Port Target on Primary or the other Secondary Port
Master on Secondary
Target not on Primary nor the other Secondary Port
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15.2
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C7300A complies with the ordering rules put forth in the PCI Local Bus Specification, Rev 2.2. The following table summarizes the ordering relationship of all the transactions through the bridge. PMW - Posted write (either memory write or memory write & invalidate) DRR - Delayed read request (all memory read, I/O read & configuration read) DWR - Delayed write request (I/O write & configuration write, memory write to certain location) DRC - Delayed read completion (all memory read, I/O read & configuration read) DWC - Delayed write completion (I/O write & configuration write, memory write to ccertain location Cycle type shown on each row is the subsequent cycle after the previous shown on the column.
Can Row Pass Column? PMW (Row 1) DRR (Row 2) DWR (Row 3) DRC (Row 4) DWC (Row 5) PMW Column 1 No No No No Yes DRR Column 2 Yes No No Yes Yes DWR Column 3 Yes No No Yes Yes DRC Column 4 Yes Yes Yes No No DWC Column 5 Yes Yes Yes No No
In Row 1 Column 1, PMW cannot pass the previous PMW and that means they must complete on the target bus in the order in which they were received in the initiator bus. In Row 2 Column1,DRR cannot pass the previous PMW and that means the previous PMW heading to the same direction must be completed before the DRR can be attempted on the target bus. In Row 1 Column 2, PMW can pass the previous DRR as long as the DRR reaches the head of the delayed transaction queue.
15.3
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)
MASTER ABORT
Master abort indicates that when PI7C7300A acts as a master and receives no response (i.e., no target asserts DEVSEL# or S1_DEVSEL# or S2_DEVSEL#) from a target, the bridge deasserts FRAME# and then deasserts IRDY#.
15.3.1
15.3.2
PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR, S1_PAR, and S2_PAR signals. Parity should be even (i. e. an even number of`1's) across AD, CBE, and PAR. Parity information on PAR is valid the cycle after AD and CBE are Page 93 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION valid. For reads, even parity must be generated using the initiators CBE signals combined with the read data. Again, the PAR signal corresponds to read data from the previous data phase cycle.
15.3.3
REPORTING PARITY ERRORS
For all address phases, if a parity error is detected, the error should be reported on the P_SERR# signal by asserting P_SERR# for one cycle and then 3-stating two cycles after the bad address. P_SERR# can only be asserted if bit 6 and 8 in the Command Register are both set to 1. For write data phases, a parity error should be reported by asserting the P_PERR# signal two cycles after the data phase and should remain asserted for one cycle when bit 6 in the Command register is set to a 1. The target reports any type of data parity errors during write cycles, while the master reports data parity errors during read cycles. Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim the bus (P_DEVSEL# remains inactive) and the cycle will then terminate with a Master Abort. When the bridge is acting as master, a data parity error during a read cycle results in the bridge master initiating a Master Abort.
15.3.4
SECONDARY IDSEL MAPPING
When PI7C7300A detects a Type 1 configuration transaction for a device connected to the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11] as a device number. This is translated to S1_AD[31:16] or S2_AD[31:16] by PI7C7300A.
16
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support boundary scan in PI7C7300A for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST#. All digital input, output, input/output pins are tested except TAP pins and clock pin. The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers including Bypass, Device Identification and Boundary Scan registers. The TAP controller is a synchronous 16-state machine driven by the Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the PCI resource is operating PCI bus cycles. PI7C7300A implements 3 basic instructions: BYPASS, SAMPLE/PRELOAD, and EXTEST.
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16.1
BOUNDARY SCAN ARCHITECTURE
Boundary-scan test logic consists of a boundary-scan register and support logic. These are accessed through a Test Access Port (TAP). The TAP provides a simple serial interface that allows all processor signal pins to be driven and/or sampled, thereby providing direct control and monitoring of processor pins at the system level. This mode of operation is valuable for design debugging and fault diagnosis since it permits examination of connections not normally accessible to the test system. The following subsections describe the boundary-scan test logic elements: TAP pins, instruction register, test data registers and TAP controller. Error! Reference source not found. illustrates how these pieces fit together to form the JTAG unit. Figure 16-1 TEST ACCESS PORT BLOCK DIAGRAM
16.1.1
TAP PINS
The PI7C7300A's TAP pins form a serial port composed of four input connections (TMS, TCK, TRST# and TDI) and one output connection (TDO). These pins are described in Table 16-1. The TAP pins provide access to the instruction register and the test data registers.
16.1.2
INSTRUCTION REGISTER
The Instruction Register (IR) holds instruction codes. These codes are shifted in through the Test Data Input (TDI) pin. The instruction codes are used to select the specific test operation to be performed and the test data register to be accessed. The instruction register is a parallel-loadable, master/slave-configured 4-bit wide, serialshift register with latched outputs. Data is shifted into and out of the IR serially through the TDI pin clocked by the rising edge of TCK. The shifted-in instruction becomes active upon latching from the master stage to the slave stage. At that time the IR outputs along Page 95 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION with the TAP finite state machine outputs are decoded to select and control the test data register selected by that instruction. Upon latching, all actions caused by any previous instructions terminate. The instruction determines the test to be performed, the test data register to be accessed, or both. The IR is two bits wide. When the IR is selected, the most significant bit is connected to TDI, and the least significant bit is connected to TDO. The value presented on the TDI pin is shifted into the IR on each rising edge of TCK. The TAP controller captures fixed parallel data (1101 binary). When a new instruction is shifted in through TDI, the value 1101(binary) is always shifted out through TDO, least significant bit first. This helps identify instructions in a long chain of serial data from several devices. Upon activation of the TRST# reset pin, the latched instruction asynchronously changes to the id code instruction. When the TAP controller moves into the test state other than by reset activation, the opcode changes as TDI shifts, and becomes active on the falling edge of TCK.
16.2
BOUNDARY-SCAN INSTRUCTION SET
The PI7C7300A supports three mandatory boundary-scan instructions (bypass, sample/preload and extest). The table shown below lists the PI7C7300A's boundary-scan instruction codes. The "reserved" code should not be used.
Instruction Code (binary) 0000 0001 Instruction Name EXTEST SAMPLE/PRELOAD Instruction Code (binary) 0101 1111 Instruction Name Reserved Bypass
Table 16-1 TAP PINS
Instruction Requisite Extest IEEE 1149.1 Required / Opcode (binary) 0000 Description Extest initiates testing of external circuitry, typically board-level interconnects and off chip circuitry. Extest connects the boundary-scan register between TDI and TDO. When Extest is selected, all output signal pin values are driven by values shifted into the boundary-scan register and may change only of the falling edge of TCK. Also, when extest is selected, all system input pin states must be loaded into the boundary-scan register on the rising-edge of TCK. Sample/preload performs two functions: 1. A snapshot of the sample instruction is captured on the rising edge of TCK without interfering with normal operation. The instruction causes boundary-scan register cells associated with outputs to sample the value being driven. 2. On the falling edge of TCK, the data held in the boundary-scan cells is transferred to the slave register cells. Typically, the slave latched data is applied to the system outputs via the extest instruction. Reserved Bypass instruction selects the one-bit bypass register between TDI and TDO pins. 0 (binary) is the only instruction that accesses the bypass register. While this instruction is in effect, all other test data registers have no effect on system operation. Test data registers with both test and system functionality perform their system functions when this instruction is selected.
Sample/preload IEEE 1149.1 Required
0001
Idcode IEEE 1149.1 Required Bypass IEEE 1149.1 Required
0101 1111
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16.3
TAP TEST DATA REGISTERS
The PI7C7300A contains two test data registers (bypass and boundary-scan). Each test data register selected by the TAP controller is connected serially between TDI and TDO. TDI is connected to the test data register's most significant bit. TDO is connected to the least significant bit. Data is shifted one bit position within the register towards TDO on each rising edge of TCK. While any register is selected, data is transferred from TDI to TDO without inversion. The following sections describe each of the test data registers.
16.4
BYPASS REGISTER
The required bypass register, a one-bit shift register, provides the shortest path between TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test data to and from other components on the board. This path can be selected when no test operation is being performed on the PI7C7300A.
16.5
BOUNDARY-SCAN REGISTER
The boundary-scan register contains a cell for each pin as well as control cells for I/O and the high-impedance pin. Table 16-2 shows the bit order of the PI7C7300A boundary-scan register. All table cells that contain "Control" select the direction of bi-directional pins or high-impedance output pins. When a "0" is loaded into the control cell, the associated pin(s) are highimpedance or selected as input. The boundary-scan register is a required set of serial-shiftable register cells, configured in master/slave stages and connected between each of the PI7C7300A's pins and on-chip system logic. The VDD, GND, PLL, AGND, AVDD and JTAG pins are NOT in the boundary-scan chain. The boundary-scan register cells are dedicated logic and do not have any system function. Data may be loaded into the boundary-scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory sample/preload and extest instructions. Parallel loading takes place on the rising edge of TCK. Data may be scanned into the boundary-scan register serially via the TDI serial input pin, clocked by the rising edge of TCK. When the required data has been loaded into the master-cell stages, it can be driven into the system logic at input pins or onto the output pins on the falling edge of TCK state. Data may also be shifted out of the boundary-scan register by means of the TDO serial output pin at the falling edge of TCK.
16.6
TAP CONTROLLER
The TAP (Test Access Port) controller is a 4-state synchronous finite state machine that controls the sequence of test logic operations. The TAP can be controlled via a bus Page 97 OF 109 09/25/03 Revision 1.09
PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION master. The bus master can be either automatic test equipment or a component (i.e., PLD) that interfaces to the TAP. The TAP controller changes state only in response to a rising edge of TCK. The value of the test mode state (TMS) input signal at a rising edge of TCK controls the sequence of state changes. The TAP controller is initialized after power-up by applying a low to the TRST# pin. In addition, the TAP controller can be initialized by applying a high signal level on the TMS input for a minimum of five TCK periods. For greater detail on the behavior of the TAP controller, test logic in each controller state and the state machine and public instructions, refer to the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture document (available from the IEEE). Table 16-2 JTAG BOUNDARY REGISTER ORDER
Order 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Pin Names ENUM# ENUM# HS_EN S_CFN# S1_EN S2_EN SCAN_TM# SCAN_EN PLL_TM BYPASS S2_M66EN P_RESET# P_GNT# P_REQ# P_REQ# P_AD[30] P_AD[30] P_AD[31] P_AD[31] P_AD[27] P_AD[27] P_AD[26] P_AD[26] P_AD[28] P_AD[28] P_AD[29] P_AD[29] P_CBE[3] P_CBE[3] P_AD[24] P_AD[24] P_AD[25] P_AD[25] P_AD[23] P_AD[23] P_AD[22] P_AD[22] P_IDSEL P_AD[21] P_AD[21] P_AD[20] P_AD[20] P_AD[19] P_AD[19] P_AD[18] P_AD[18] Type output control input input input input input input input input input input input output control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control input bidir control bidir control bidir control bidir control Order 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Pin Names P_STOP# P_PERR# P_PERR# P_LOCK# P_SERR# P_SERR# P_AD[13] P_AD[13] P_AD[14] P_AD[14] P_AD[11] P_AD[11] P_AD[15] P_AD[15] P_AD[12] P_AD[12] P_AD[8] P_AD[8] P_CBE[1] P_CBE[1] P_AD[9] P_AD[9] P_AD[5] P_AD[5] P_M66EN P_AD[6] P_AD[6] P_AD[2] P_AD[2] P_PAR P_PAR P_AD[0] P_AD[0] P_CBE[0] P_CBE[0] P_AD[7] P_AD[7] P_AD[10] P_AD[10] P_AD[1] P_AD[1] P_AD[3] P_AD[3] P_AD[4] P_AD[4] S1_AD[0] Type control bidir control input output control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control input bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir
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Order 46 47 48 49 50 51 52 53 54 55 56 57 58 59 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin Names P_AD[17] P_AD[17] P_AD[16] P_AD[16] P_CBE[2] P_CBE[2] P_FRAME# P_FRAME# P_IRDY# P_IRDY# P_TRDY#
P_DEVSEL#/P_TRDY#
P_DEVSEL# P_STOP# S1_AD[7] S1_AD[6] S1_AD[6] S1_AD[8] S1_AD[8] S1_AD[9] S1_AD[9] S1_AD[10] S1_AD[10] S1_AD[11] S1_AD[11] S1_AD[12] S1_AD[12] S1_AD[14] S1_AD[14] S1_AD[13] S1_AD[13] S1_AD[15] S1_AD[15] S1_SERR# S1_PAR S1_PAR S1_CBE[1] S1_CBE[1] S1_DEVSEL#
S1_DEVSEL#/S1_TRDY#
S1_STOP# S1_STOP# S1_LOCK# S1_LOCK# S1_PERR# S1_PERR# S1_FRAME# S1_FRAME# S1_IRDY# S1_IRDY# S1_TRDY# S1_AD[17] S1_AD[17] S1_AD[16] S1_AD[16] S1_AD[20] S1_AD[20] S1_CBE[2] S1_CBE[2] S1_AD[19] S1_AD[19] S1_CBE[3] S1_CBE[3]
Type bidir control bidir control bidir control bidir control bidir control bidir control bidir bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control input bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir bidir control bidir control bidir control bidir control bidir control bidir control
Order 106 107 108 109 110 111 112 113 114 115 116 117 118 119 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230
Pin Names S1_AD[0] S1_AD[1] S1_AD[1] S1_AD[2] S1_AD[2] S1_AD[5] S1_AD[5] S1_AD[3] S1_AD[3] S1_AD[4] S1_AD[4] S1_CBE[0] S1_CBE[0] S1_AD[7] S1_AD[28] S1_AD[30] S1_AD[30] S1_AD[31] S1_AD[31] S1_AD[27] S1_AD[27] S1_AD[24] S1_AD[24] S1_AD[18] S1_AD[18] S1_GNT#[0] S1_GNT#[0] S1_REQ#[0] S1_REQ#[1] S1_GNT#[1] S1_GNT#[2] S1_REQ#[2] S1_REQ#[3] S1_GNT#[3] S1_GNT#[4] S1_REQ#[4] S1_REQ#[5] S1_GNT#[5] S1_GNT#[6] S1_REQ#[6] S1_REQ#[7] S1_GNT#[7] S1_RESET# S2_AD[0] S2_AD[0] S2_AD[1] S2_AD[1] S2_AD[2] S2_AD[2] S2_AD[3] S2_AD[3] S2_AD[4] S2_AD[4] S2_AD[5] S2_AD[5] S2_AD[6] S2_AD[6] S2_AD[7] S2_AD[7] S2_CBE[0] S2_CBE[0] S2_AD[8] S2_AD[8]
Type control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control output control input input output output input input output output input input output output input input output output bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control
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Order 169 170 171 172 173 174 175 176 177 178 179 180 181 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 Order 272 273 274 275 276 277 278 279 280 281 Pin Names S1_AD[23] S1_AD[23] S1_AD[26] S1_AD[26] S1_AD[22] S1_AD[22] S1_AD[25] S1_AD[25] S1_AD[29] S1_AD[29] S1_AD[21] S1_AD[21] S1_AD[28] S2_AD[15] S2_AD[15] S2_PAR S2_PAR S2_SERR# S2_LOCK# S2_LOCK# S2_TRDY#
S2_DEVSEL#/S2_TRDY#
S2_STOP# S2_STOP# S2_IRDY# S2_IRDY# S2_CBE[2] S2_CBE[2] S2_AD[13] S2_AD[13] S2_AD[21] S2_AD[21] S2_PERR# S2_PERR# S2_AD[16] S2_AD[16] S2_FRAME# S2_FRAME# S2_DEVSEL# S2_AD[19] S2_AD[19] Pin Names S2_AD[17] S2_AD[17] S2_AD[18] S2_AD[18] S2_AD[20] S2_AD[20] S2_AD[22] S2_AD[22] S2_AD[24] S2_AD[24]
Type bidir control bidir control bidir control bidir control bidir control bidir control bidir bidir control bidir control input bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir bidir control Type bidir control bidir control bidir control bidir control bidir control
Order 231 232 233 234 235 236 237 238 239 240 241 242 243 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 Order 310 311 312 313 314
Pin Names S2_AD[10] S2_AD[10] S2_AD[9] S2_AD[9] S2_AD[11] S2_AD[11] S1_M66EN S2_AD[12] S2_AD[12] S2_AD[14] S2_AD[14] S2_CBE[1] S2_CBE[1] S2_AD[23] S2_AD[23] S2_CBE[3] S2_CBE[3] S2_AD[25] S2_AD[25] S2_AD[26] S2_AD[26] S2_AD[28] S2_AD[28] S2_AD[27] S2_AD[27] S2_AD[29] S2_AD[29] S2_AD[30] S2_AD[30] S2_AD[31] S2_AD[31] S2_GNT#[0] S2_GNT#[0] S2_REQ#[0] S2_REQ#[1] S2_GNT#[1] S2_GNT#[2] S2_REQ#[2] S2_REQ#[3] S2_GNT#[3] S2_GNT#[4] Pin Names S2_REQ#[4] S2_REQ#[5] S2_GNT#[5] S2_GNT#[6] S2_REQ#[6]
Type bidir control bidir control bidir control Input bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir control output control input input output output input input output output Type input input output output input
17
ELECTRICAL AND TIMING SPECIFICATIONS
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17.1
MAXIMUM RATINGS
(Above which the useful life may be impaired. For user guidelines, not tested).
Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potentials (Inputs and AVCC, VDD only] DC Input Voltage -65C to 150C -40C to 85C -0.3V to 3.6V -0.5V to 3.6V
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
17.2
3.3V DC SPECIFICATIONS
Symbol VDD, AVCC Vih Vil Vih Vil Vipu Iil Voh Vol Voh Vol Cin CCLK CIDSEL Lpin Parameter Supply Voltage Input HIGH Voltage Input LOW Voltage CMOS Input HIGH Voltage CMOS Input LOW Voltage Input Pull-up Voltage Input Leakage Current Output HIGH Voltage Output LOW Voltage CMOS Output HIGH Voltage CMOS Output LOW Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance Pin Inductance Condition Min. 3 0.5 VDD -0.5 0.7 VDD -0.5 0.7 VDD 0 < Vin < VDD Iout = -500A Iout = 1500A Iout = -500A Iout = 1500A 0.9VDD 0.1 VDD VDD - 0.5 0.5 10 12 8 20 Max. 3.6 VDD + 0.5 0.3 VDD VDD + 0.5 0.3 VDD 10 Units V V V V V V A V V V V pF pF pF nH Notes
5
3 3 1 1 3 3 3 3 2 2 3 3 3 3
Notes:
1. 2. CMOS Input pins: S_CFN#, TCK, TMS, TDI, TRST#, SCAN_EN, SCAN_TM# CMOS Output pin: TDO PCI pins: P_AD[31:0], P_CBE[3:0], P_PAR, P_FRAME#, P_IRDY#, P_TRDY#, P_DEVSEL#, P_STOP#, P_LOCK#, PIDSEL#, P_PERR#, P_SERR#, P_REQ#, P_GNT#, P_RESET#, S1_AD[31:0], S2_AD[31:0], S1_CBE[3:0], S2_CBE[3:0], S1_PAR, S2_PAR, S1_FRAME#, S2_FRAME#, S1_IRDY#, S2_IRDY#, S1_TRDY#, S2_TRDY#, S1_DEVSEL#, S2_DEVSEL#, S1_STOP#, S2_STOP#, S1_LOCK#, S2_LOCK#, S1_PERR#, S2_PERR#, S1_SERR#, S2_SERR#, S1_REQ[7:0]#, S2_REQ[6:0]#, S1_GNT[7:0]#, S2_GNT[6:0], S1_RESET#, S2_RESET#, S1_EN, S2_EN, HSLED, HS_SW#, HS_EN, ENUM#.
3.
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17.3
3.3V AC SPECIFICATIONS
Figure 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS
Symbol Tsu Tsu(ptp) Th Tval Tval(ptp) Ton Toff
Parameter Input setup time to CLK - bused signals 1,2,3 Input setup time to CLK - point-to-point 1,2,3 Input signal hold time from CLK 1,2 CLK to signal valid delay - bused signals 1,2,3 CLK to signal valid delay - point-to-point 1,2,3 Float to active delay 1,2 Active to float delay 1,2
66 MHz Min. Max. 3 5 0 2 6 2 6 2 14
33 MHz Min. Max. 7 10, 124 0 2 11 2 12 2 28
Units
ns
1. 2. 3.
See Figure 17-1 PCI Signal Timing Measurement Conditions. All primary interface signals are synchronized to P_CLK. All secondary interface signals are synchronized to either S1_CLKOUT or S2_CLKOUT. Point-to-point signals are P_REQ#, S1_REQ#[7:0], S2_REQ#[6:0], P_GNT#, S1_GNT#[7:0], S2_GNT#[6:0], HSLED, HS_SW#, HS_EN, and ENUM#. Bused signals are P_AD, P_BDE#, P_PAR, P_PERR#, P_SERR#, P_FRAME#, P_IRDY#, P_TRDY#, P_LOCK#, P_DEVSEL#, P_STOP#, P_IDSEL, S1_AD, S1_CBE#, S1_PAR, S1_PERR#, S1_SERR#, S1_FRAME#, S1_IRDY#, S1_TRDY#, S1_LOCK#, S1_devsel#, S1_STOP#, S2_AD, S2_CBE#, S2_PAR, S2_PERR#, S2_SERR#, S2_FRAME#, S2_IRDY#, S2_TRDY#, S2_LOCK#, S2_DEVSEL#, and S2_STOP#. REQ# signals have a setup of 10 and GNT# signals have a setup of 12.
4.
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17.4
PRIMARY AND SECONDARY BUSES AT 66MHz CLOCK TIMING
Symbol TSKEW TSKEW TDELAY TDELAY TCYCLE TCYCLE THIGH THIGH TLOW TLOW Parameter SKEW among S1_CLKOUT[7:0] SKEW among S2_CLKOUT[6:0] DELAY between PCLK and S1_CLKOUT[7:0] DELAY between PCLK and S2_CLKOUT[6:0] PCLK, S1_CLKOUT[7:0] cycle time PCLK, S2_CLKOUT[6:0] cycle time PCLK, S1_CLKOUT[7:0] HIGH time PCLK, S2_CLKOUT[6:0] HIGH time PCLK, S1_CLKOUT[7:0] LOW time PCLK, S_CLKOUT[6:0] LOW time Condition Min. 0 0 3.3 3.3 15 15 6 6 6 6 Max. 250 250 4.9 4.9 30 30 Units ps
20pF load 20pF load
ns
17.5
PRIMARY AND SECONDARY BUSES AT 33MHz CLOCK TIMING
Symbol TSKEW TSKEW TDELAY TDELAY TCYCLE TCYCLE THIGH THIGH TLOW TLOW Parameter SKEW among S1_CLKOUT[7:0] SKEW among S2_CLKOUT[6:0] DELAY between PCLK and S1_CLKOUT[7:0] DELAY between PCLK and S2_CLKOUT[6:0] PCLK, S1_CLKOUT[7:0] cycle time PCLK, S2_CLKOUT[6:0] cycle time PCLK, S1_CLKOUT[7:0] HIGH time PCLK, S2_CLKOUT[6:0] HIGH time PCLK, S1_CLKOUT[7:0] LOW time PCLK, S2_CLKOUT[6:0] LOW time Condition Min. 0 0 3.3 3.3 30 30 11 11 11 11 Max. 250 250 4.9 4.9 Units ps
20pF load 20pF load
ns
17.6
POWER CONSUMPTION
Parameter Typical Units Power Consumption 2178 mW Supply Current, ICC 660 mA Note: Typical values are at VCC = 3.3V, TA = 25C, and all three ports running at 66MHz.
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18
272-PIN PBGA PACKAGE FIGURE
Figure 18-1 272-PIN PBGA PACKAGE
TOP
BOTTOM
Thermal Characteristics can be found on the web: http://www.pericom.com/packaging/mechanicals.php
18.1
PART NUMBER ORDERING INFORMATION
Part Number PI7C7300ANA Pin - Package 272 - PBGA Temperature -40C to 85C
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
APPENDIX A: PI7C7300A EVALUATION BOARD USER'S MANUAL GENERAL INFORMATION
1. 2. Please make sure you have included with your PI7C7300A evaluation board, the five-page schematic and the preliminary specification for the PI7C7300A. Check all jumpers for proper settings: Pin Name S_CFN# S1_EN S2_EN SCAN_EN PLL_TM BYPASS 3. 4. 5. Jumper JP4 JP5 JP6 JP7 JP8 JP9 Function Internal Arbiter Enable S1 Bus Enable S2 Bus Enable Scan Control PLL test mode disable PLL disable Position 1-2 (0) 2-3 (1) 2-3 (1) 1-2 (0) 1-2 (0) 2-3 (1)
Check and make sure there are no shorts between power (3.3V, 5V, 12V, and -12V) and ground. Plug evaluation board in any PCI slot on your system. Make sure your system is powered off before doing so. Connect any PCI devices on the secondary slots of the evaluation board. Be careful that the orientation of the card is correct (see Diagram A).
Diagram A
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
GENERAL INFORMATION (continued)
6. Turn on the power for the system. Your OS should already have drivers for the PI7C7300A evaluation board. In Win9X, Plug and Play should detect the device as a PCI-to-PCI bridge. The system may prompt you for the Win9X CD for the drivers. The OS will detect two PCI-to-PCI bridges as the PI7C7300A has two secondary PCI buses. In Win NT, you should not have to install drivers. Install drivers for any PCI devices you have attached to the evaluation board. If any of the steps are unclear or were unsuccessful, please contact your Pericom support person at 408-435-0800. Thank for evaluating Pericom Semiconductor Corporation's products.
7. 8. 9.
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FREQUENTLY ASKED QUESTIONS
! What is the function of SCAN_EN?
SCAN_EN is for a full scan test or S_CLKIN select. During SCAN mode, SCAN_EN will be driven to logic "0" or "logic "1" depending on functionality. During normal mode, if SCAN_EN is connected to logic "0" (JP7 in the 1-2 position), S_CLKIN will be used for PLL test only when PL_TM is active.
!
What is the function of SCAN_TM#?
SCAN_TM# is for full scan test and power on reset for the PLL. SCAN_TM# should be connected to logic "1" or to an RC path (R1 and C13) during normal operation.
!
How do you use the external arbiter?
a) Disable the on chip arbiter by connecting S_CFN to logic "1" (JP4 in the 2-3 position). b) Use S1_REQ#[0] as GRANT and S1_GNT#[0] as REQUEST on the S1 bus. c) Use S2_REQ#[0] as GRANT and S2_GNT#[0] as REQUEST on the S2 bus.
!
What is the purpose of having JP1, JP2, and JP3?
JP1, JP2, and JP3 are designed for easy access to the primary bus signals. You may connect any of these pins to an oscilloscope or a logic analyzer for observation. No connection is required for normal operation. The following table indicates which bus signals correspond to which pins.
1 JP2 JP3 JP1 REQ AD31 GNT
2 AD29 AD28 AD30
3 AD26 AD25 AD27
4 CBE3 AD23 AD24
5 AD21 AD20 AD22
6 AD21 AD20 AD22
7 CBE2 FRAME AD24
8 IRDY DVSEL IRDY
9 LOCK PERR STOP
10 PAR CBE1 SERR
11 AD14 AD13 AD15
12 AD11 AD10 AD12
13 CBE0 AD8 AD9
14 AD6 AD4 AD7
15 AD5 AD2 AD3
16 AD0 GND AD1
!
What is the purpose for having U17, U19, and U20?
U17, U19, and U20 are designed for easy access to the digital ground planes for observation.
!
How is the evaluation board constructed?
The evaluation board is a six-layer PCB. The top and bottom layers (1 and 6) are for signals, power, and ground routing. Layer 2 and layer 5 are ground planes. Layer 3 is a digital 3.3V power plane. Layer 4 is a digital 5V power plane with an island of analog 3.3V power.
!
What is the function of S_CLKIN?
The S_CLKIN pin is a test pin for the on chip PLL when PLL_TM is set to logic "1".
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
!
What clock frequency combinations does the PI7C7300A support?
Primary 66MHz 66MHz 66MHz 66MHz 33MHz 50MHz 50MHz 50MHz 50MHz 25MHz Secondary 1 66MHz 66MHz 33MHz 33MHz 33MHz 50MHz 50MHz 25MHz 25MHz 25MHz Secondary 2 66MHz 33MHz 66MHz 33MHz 33MHz 50MHz 25MHz 50MHz 25MHz 25MHz
!
How are the JTAG signals being connected?
The JTAG signals consist of TRST#, TCK, TMS, TDI, and TDO. All the mentioned signals have weak internal pull-up connections. Therefore, no connection is needed if you want the JTAG circuit to be disabled. If you want to activate the JTAG circuit, you need to connect all five signals according to the JTAG specification (IEEE 1149).
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PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION NOTES:
Page 109 OF 109 09/25/03 Revision 1.09

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